	.data
	.align	2
	.globl	class_nameTab
	.globl	Main_protObj
	.globl	Int_protObj
	.globl	String_protObj
	.globl	bool_const0
	.globl	bool_const1
	.globl	_int_tag
	.globl	_bool_tag
	.globl	_string_tag
	.globl	_MemMgr_INITIALIZER
	.globl	_MemMgr_COLLECTOR
	.globl	_MemMgr_TEST
_MemMgr_INITIALIZER:
	.word	_NoGC_Init
_MemMgr_COLLECTOR:
	.word	_NoGC_Collect
_MemMgr_TEST:
	.word	0
_int_tag:
	.word	1
_bool_tag:
	.word	2
_string_tag:
	.word	3
str_const75:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const1
	.byte	0, 0, 0, 0
str_const74:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const2
	.ascii	"Main"
	.byte	0, 0, 0, 0
str_const73:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const2
	.ascii	"Term"
	.byte	0, 0, 0, 0
str_const72:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const3
	.ascii	"App"
	.byte	0
str_const71:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const4
	.ascii	"Lambda"
	.byte	0, 0
str_const70:
	.word	3
	.word	7
	.word	String_dispatch
	.word	int_const5
	.ascii	"Variable"
	.byte	0, 0, 0, 0
str_const69:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const2
	.ascii	"Expr"
	.byte	0, 0, 0, 0
str_const68:
	.word	3
	.word	8
	.word	String_dispatch
	.word	int_const6
	.ascii	"LambdaListRef"
	.byte	0, 0, 0
str_const67:
	.word	3
	.word	8
	.word	String_dispatch
	.word	int_const7
	.ascii	"LambdaListNE"
	.byte	0, 0, 0, 0
str_const66:
	.word	3
	.word	7
	.word	String_dispatch
	.word	int_const8
	.ascii	"LambdaList"
	.byte	0, 0
str_const65:
	.word	3
	.word	7
	.word	String_dispatch
	.word	int_const9
	.ascii	"VarListNE"
	.byte	0, 0, 0
str_const64:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const10
	.ascii	"VarList"
	.byte	0
str_const63:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const11
	.ascii	"IO"
	.byte	0, 0
str_const62:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const4
	.ascii	"String"
	.byte	0, 0
str_const61:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const2
	.ascii	"Bool"
	.byte	0, 0, 0, 0
str_const60:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const3
	.ascii	"Int"
	.byte	0
str_const59:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const4
	.ascii	"Object"
	.byte	0, 0
str_const58:
	.word	3
	.word	7
	.word	String_dispatch
	.word	int_const8
	.ascii	"_prim_slot"
	.byte	0, 0
str_const57:
	.word	3
	.word	7
	.word	String_dispatch
	.word	int_const9
	.ascii	"SELF_TYPE"
	.byte	0, 0, 0
str_const56:
	.word	3
	.word	7
	.word	String_dispatch
	.word	int_const9
	.ascii	"_no_class"
	.byte	0, 0, 0
str_const55:
	.word	3
	.word	8
	.word	String_dispatch
	.word	int_const6
	.ascii	"<basic class>"
	.byte	0, 0, 0
str_const54:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const10
	.ascii	"\n};\n};\n"
	.byte	0
str_const53:
	.word	3
	.word	11
	.word	String_dispatch
	.word	int_const12
	.ascii	"  main() : EvalObject {\n"
	.byte	0, 0, 0, 0
str_const52:
	.word	3
	.word	8
	.word	String_dispatch
	.word	int_const6
	.ascii	"class Main {\n"
	.byte	0, 0, 0
str_const51:
	.word	3
	.word	17
	.word	String_dispatch
	.word	int_const13
	.ascii	"(*Generated by lam.cl (Jeff Foster, March 2000)*)\n"
	.byte	0, 0
str_const50:
	.word	3
	.word	16
	.word	String_dispatch
	.word	int_const14
	.ascii	"\n------------------cut here------------------\n"
	.byte	0, 0
str_const49:
	.word	3
	.word	10
	.word	String_dispatch
	.word	int_const15
	.ascii	"Generating code for "
	.byte	0, 0, 0, 0
str_const48:
	.word	3
	.word	20
	.word	String_dispatch
	.word	int_const16
	.ascii	"  apply(y : EvalObject) : EvalObject { { abort(); self; } };\n"
	.byte	0, 0, 0
str_const47:
	.word	3
	.word	19
	.word	String_dispatch
	.word	int_const17
	.ascii	"  init(p : Closure) : Closure {{ parent <- p; self; }};\n"
	.byte	0, 0, 0, 0
str_const46:
	.word	3
	.word	12
	.word	String_dispatch
	.word	int_const18
	.ascii	"  get_x() : EvalObject { x };\n"
	.byte	0, 0
str_const45:
	.word	3
	.word	14
	.word	String_dispatch
	.word	int_const19
	.ascii	"  get_parent() : Closure { parent };\n"
	.byte	0, 0, 0
str_const44:
	.word	3
	.word	9
	.word	String_dispatch
	.word	int_const20
	.ascii	"  x : EvalObject;\n"
	.byte	0, 0
str_const43:
	.word	3
	.word	10
	.word	String_dispatch
	.word	int_const15
	.ascii	"  parent : Closure;\n"
	.byte	0, 0, 0, 0
str_const42:
	.word	3
	.word	14
	.word	String_dispatch
	.word	int_const21
	.ascii	"class Closure inherits EvalObject {\n"
	.byte	0, 0, 0, 0
str_const41:
	.word	3
	.word	16
	.word	String_dispatch
	.word	int_const14
	.ascii	"  eval() : EvalObject { { abort(); self; } };\n"
	.byte	0, 0
str_const40:
	.word	3
	.word	12
	.word	String_dispatch
	.word	int_const22
	.ascii	"class EvalObject inherits IO {\n"
	.byte	0
str_const39:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const2
	.ascii	" =>\n"
	.byte	0, 0, 0, 0
str_const38:
	.word	3
	.word	8
	.word	String_dispatch
	.word	int_const6
	.ascii	"beta-reduce: "
	.byte	0, 0, 0
str_const37:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const0
	.ascii	"z"
	.byte	0, 0, 0
str_const36:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const0
	.ascii	"y"
	.byte	0, 0, 0
str_const35:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const0
	.ascii	"x"
	.byte	0, 0, 0
str_const34:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const10
	.ascii	"  esac)"
	.byte	0
str_const33:
	.word	3
	.word	17
	.word	String_dispatch
	.word	int_const23
	.ascii	"    o : Object => { abort(); new EvalObject; };\n"
	.byte	0, 0, 0, 0
str_const32:
	.word	3
	.word	12
	.word	String_dispatch
	.word	int_const22
	.ascii	"    c : Closure => c.apply(y);\n"
	.byte	0
str_const31:
	.word	3
	.word	8
	.word	String_dispatch
	.word	int_const7
	.ascii	"  case x of\n"
	.byte	0, 0, 0, 0
str_const30:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const2
	.ascii	" in\n"
	.byte	0, 0, 0, 0
str_const29:
	.word	3
	.word	10
	.word	String_dispatch
	.word	int_const24
	.ascii	"     y : EvalObject <- "
	.byte	0
str_const28:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const11
	.ascii	",\n"
	.byte	0, 0
str_const27:
	.word	3
	.word	10
	.word	String_dispatch
	.word	int_const24
	.ascii	"(let x : EvalObject <- "
	.byte	0
str_const26:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const11
	.ascii	"))"
	.byte	0, 0
str_const25:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const3
	.ascii	")@("
	.byte	0
str_const24:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const11
	.ascii	"(("
	.byte	0, 0
str_const23:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const3
	.ascii	"};\n"
	.byte	0
str_const22:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const25
	.ascii	";}};\n"
	.byte	0, 0, 0
str_const21:
	.word	3
	.word	8
	.word	String_dispatch
	.word	int_const26
	.ascii	"      x <- y;\n"
	.byte	0, 0
str_const20:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const4
	.byte	92
	.ascii	"n\");\n"
	.byte	0, 0
str_const19:
	.word	3
	.word	13
	.word	String_dispatch
	.word	int_const27
	.ascii	"    { out_string(\"Applying closure "
	.byte	0
str_const18:
	.word	3
	.word	14
	.word	String_dispatch
	.word	int_const28
	.ascii	"  apply(y : EvalObject) : EvalObject {\n"
	.byte	0
str_const17:
	.word	3
	.word	10
	.word	String_dispatch
	.word	int_const15
	.ascii	" inherits Closure {\n"
	.byte	0, 0, 0, 0
str_const16:
	.word	3
	.word	8
	.word	String_dispatch
	.word	int_const6
	.ascii	"class Closure"
	.byte	0, 0, 0
str_const15:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const4
	.ascii	"self))"
	.byte	0, 0
str_const14:
	.word	3
	.word	8
	.word	String_dispatch
	.word	int_const6
	.ascii	"new Closure))"
	.byte	0, 0, 0
str_const13:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const10
	.ascii	").init("
	.byte	0
str_const12:
	.word	3
	.word	8
	.word	String_dispatch
	.word	int_const6
	.ascii	"((new Closure"
	.byte	0, 0, 0
str_const11:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const0
	.ascii	"."
	.byte	0, 0, 0
str_const10:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const0
	.byte	92
	.byte	0, 0, 0
str_const9:
	.word	3
	.word	6
	.word	String_dispatch
	.word	int_const10
	.ascii	"get_x()"
	.byte	0
str_const8:
	.word	3
	.word	11
	.word	String_dispatch
	.word	int_const29
	.ascii	"Error:  free occurrence of "
	.byte	0
str_const7:
	.word	3
	.word	8
	.word	String_dispatch
	.word	int_const6
	.ascii	"get_parent()."
	.byte	0, 0, 0
str_const6:
	.word	3
	.word	16
	.word	String_dispatch
	.word	int_const30
	.ascii	"\nError: Expr is pure virtual; can't gen_code\n"
	.byte	0, 0, 0
str_const5:
	.word	3
	.word	16
	.word	String_dispatch
	.word	int_const31
	.ascii	"\nError: Expr is pure virtual; can't substitute\n"
	.byte	0
str_const4:
	.word	3
	.word	17
	.word	String_dispatch
	.word	int_const23
	.ascii	"\nError: Expr is pure virtual; can't beta-reduce\n"
	.byte	0, 0, 0, 0
str_const3:
	.word	3
	.word	16
	.word	String_dispatch
	.word	int_const31
	.ascii	"\nError: Expr is pure virtual; can't print self\n"
	.byte	0
str_const2:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const0
	.ascii	" "
	.byte	0, 0, 0
str_const1:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const0
	.ascii	"\n"
	.byte	0, 0, 0
str_const0:
	.word	3
	.word	10
	.word	String_dispatch
	.word	int_const32
	.ascii	"_tests/advanced/lam.cl"
	.byte	0, 0
int_const32:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	22
int_const31:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	47
int_const30:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	45
int_const29:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	27
int_const28:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	39
int_const27:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	35
int_const26:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	14
int_const25:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	5
int_const24:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	23
int_const23:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	48
int_const22:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	31
int_const21:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	36
int_const20:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	18
int_const19:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	37
int_const18:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	30
int_const17:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	56
int_const16:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	61
int_const15:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	20
int_const14:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	46
int_const13:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	50
int_const12:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	24
int_const11:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	2
int_const10:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	7
int_const9:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	9
int_const8:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	10
int_const7:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	12
int_const6:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	13
int_const5:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	8
int_const4:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	6
int_const3:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	3
int_const2:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	4
int_const1:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	0
int_const0:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	1
bool_const1:
	.word	2
	.word	4
	.word	Object_dispatch
	.word	1
bool_const0:
	.word	2
	.word	4
	.word	Object_dispatch
	.word	0
class_nameTab:
	.word	str_const59
	.word	str_const60
	.word	str_const61
	.word	str_const62
	.word	str_const63
	.word	str_const66
	.word	str_const68
	.word	str_const67
	.word	str_const64
	.word	str_const69
	.word	str_const73
	.word	str_const74
	.word	str_const70
	.word	str_const71
	.word	str_const72
	.word	str_const65
class_objTab:
	.word	Object_protObj
	.word	Object_init
	.word	Int_protObj
	.word	Int_init
	.word	Bool_protObj
	.word	Bool_init
	.word	String_protObj
	.word	String_init
	.word	IO_protObj
	.word	IO_init
	.word	LambdaList_protObj
	.word	LambdaList_init
	.word	LambdaListRef_protObj
	.word	LambdaListRef_init
	.word	LambdaListNE_protObj
	.word	LambdaListNE_init
	.word	VarList_protObj
	.word	VarList_init
	.word	Expr_protObj
	.word	Expr_init
	.word	Term_protObj
	.word	Term_init
	.word	Main_protObj
	.word	Main_init
	.word	Variable_protObj
	.word	Variable_init
	.word	Lambda_protObj
	.word	Lambda_init
	.word	App_protObj
	.word	App_init
	.word	VarListNE_protObj
	.word	VarListNE_init
Object_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
String_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	String.concat
	.word	String.length
	.word	String.substr
IO_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	IO.out_string
	.word	IO.out_int
	.word	IO.in_string
	.word	IO.in_int
LambdaList_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	LambdaList.isNil
	.word	LambdaList.headE
	.word	LambdaList.headC
	.word	LambdaList.headN
	.word	LambdaList.tail
	.word	LambdaList.add
LambdaListRef_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	LambdaListRef.isNil
	.word	LambdaListRef.headE
	.word	LambdaListRef.headC
	.word	LambdaListRef.headN
	.word	LambdaListRef.reset
	.word	LambdaListRef.add
	.word	LambdaListRef.removeHead
LambdaListNE_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	LambdaListNE.isNil
	.word	LambdaListNE.headE
	.word	LambdaListNE.headC
	.word	LambdaListNE.headN
	.word	LambdaListNE.tail
	.word	LambdaList.add
	.word	LambdaListNE.init
VarList_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	IO.out_string
	.word	IO.out_int
	.word	IO.in_string
	.word	IO.in_int
	.word	VarList.isNil
	.word	VarList.head
	.word	VarList.tail
	.word	VarList.add
	.word	VarList.print
Expr_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	IO.out_string
	.word	IO.out_int
	.word	IO.in_string
	.word	IO.in_int
	.word	Expr.print_self
	.word	Expr.beta
	.word	Expr.substitute
	.word	Expr.gen_code
Term_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	IO.out_string
	.word	IO.out_int
	.word	IO.in_string
	.word	IO.in_int
	.word	Term.var
	.word	Term.lam
	.word	Term.app
	.word	Term.i
	.word	Term.k
	.word	Term.s
Main_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	IO.out_string
	.word	IO.out_int
	.word	IO.in_string
	.word	IO.in_int
	.word	Term.var
	.word	Term.lam
	.word	Term.app
	.word	Term.i
	.word	Term.k
	.word	Term.s
	.word	Main.beta_reduce
	.word	Main.eval_class
	.word	Main.closure_class
	.word	Main.gen_code
	.word	Main.main
Variable_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	IO.out_string
	.word	IO.out_int
	.word	IO.in_string
	.word	IO.in_int
	.word	Variable.print_self
	.word	Variable.beta
	.word	Variable.substitute
	.word	Variable.gen_code
	.word	Variable.init
Lambda_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	IO.out_string
	.word	IO.out_int
	.word	IO.in_string
	.word	IO.in_int
	.word	Lambda.print_self
	.word	Lambda.beta
	.word	Lambda.substitute
	.word	Lambda.gen_code
	.word	Lambda.init
	.word	Lambda.apply
	.word	Lambda.gen_closure_code
App_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	IO.out_string
	.word	IO.out_int
	.word	IO.in_string
	.word	IO.in_int
	.word	App.print_self
	.word	App.beta
	.word	App.substitute
	.word	App.gen_code
	.word	App.init
VarListNE_dispatch:
	.word	Object.abort
	.word	Object.copy
	.word	Object.type_name
	.word	IO.out_string
	.word	IO.out_int
	.word	IO.in_string
	.word	IO.in_int
	.word	VarListNE.isNil
	.word	VarListNE.head
	.word	VarListNE.tail
	.word	VarList.add
	.word	VarListNE.print
	.word	VarListNE.init
Object_protObj:
	.word	0
	.word	3
	.word	Object_dispatch
Int_protObj:
	.word	1
	.word	4
	.word	Object_dispatch
	.word	0
Bool_protObj:
	.word	2
	.word	4
	.word	Object_dispatch
	.word	0
String_protObj:
	.word	3
	.word	5
	.word	String_dispatch
	.word	int_const1
	.word	0
IO_protObj:
	.word	4
	.word	3
	.word	IO_dispatch
LambdaList_protObj:
	.word	5
	.word	3
	.word	LambdaList_dispatch
LambdaListRef_protObj:
	.word	6
	.word	5
	.word	LambdaListRef_dispatch
	.word	0
	.word	0
LambdaListNE_protObj:
	.word	7
	.word	7
	.word	LambdaListNE_dispatch
	.word	0
	.word	0
	.word	0
	.word	0
VarList_protObj:
	.word	8
	.word	3
	.word	VarList_dispatch
Expr_protObj:
	.word	9
	.word	3
	.word	Expr_dispatch
Term_protObj:
	.word	10
	.word	3
	.word	Term_dispatch
Main_protObj:
	.word	11
	.word	3
	.word	Main_dispatch
Variable_protObj:
	.word	12
	.word	4
	.word	Variable_dispatch
	.word	str_const75
Lambda_protObj:
	.word	13
	.word	5
	.word	Lambda_dispatch
	.word	0
	.word	0
App_protObj:
	.word	14
	.word	5
	.word	App_dispatch
	.word	0
	.word	0
VarListNE_protObj:
	.word	15
	.word	5
	.word	VarListNE_dispatch
	.word	0
	.word	0
heap_start:
	.word	0

	.text
	.globl	Int_init
	.globl	String_init
	.globl	Bool_init
	.globl	Main_init
	.globl	Main.main
void_disp_handler:
	lw	$t1, 4 ($sp)
	jal	_dispatch_abort
void_case_handler:
	lw	$t1, 4 ($sp)
	jal	_case_abort2
# web count: 0
Object_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	j	__Object_init_epilogue
__Object_init_epilogue:
	## restoring registers
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 0
Int_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	j	__Int_init_epilogue
__Int_init_epilogue:
	## restoring registers
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 0
Bool_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	j	__Bool_init_epilogue
__Bool_init_epilogue:
	## restoring registers
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 0
String_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	j	__String_init_epilogue
__String_init_epilogue:
	## restoring registers
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 0
IO_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	j	__IO_init_epilogue
__IO_init_epilogue:
	## restoring registers
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 1
# VR0-[[0, 3)]-{0}-[2] --> $s0
LambdaList_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	jal	Object_init
	move	$a0, $s0
	j	__LambdaList_init_epilogue
__LambdaList_init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 2
# VR0-[[0, 5)]-{0}-[3, 4] --> $s0
# VR1-[[2, 4)]-{1}-[3] --> $s1
LambdaListRef_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	jal	Object_init
	li	$s1, 0
	sw	$s1, 12 ($s0)
	move	$a0, $s0
	j	__LambdaListRef_init_epilogue
__LambdaListRef_init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 2
# VR0-[[0, 5)]-{0}-[3, 4] --> $s0
# VR1-[[2, 4)]-{1}-[3] --> $s1
LambdaListNE_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	jal	LambdaList_init
	li	$s1, 0
	sw	$s1, 16 ($s0)
	move	$a0, $s0
	j	__LambdaListNE_init_epilogue
__LambdaListNE_init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 1
# VR0-[[0, 3)]-{0}-[2] --> $s0
VarList_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	jal	IO_init
	move	$a0, $s0
	j	__VarList_init_epilogue
__VarList_init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 1
# VR0-[[0, 3)]-{0}-[2] --> $s0
Expr_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	jal	IO_init
	move	$a0, $s0
	j	__Expr_init_epilogue
__Expr_init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 1
# VR0-[[0, 3)]-{0}-[2] --> $s0
Term_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	jal	IO_init
	move	$a0, $s0
	j	__Term_init_epilogue
__Term_init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 1
# VR0-[[0, 3)]-{0}-[2] --> $s0
Main_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	jal	Term_init
	move	$a0, $s0
	j	__Main_init_epilogue
__Main_init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 1
# VR0-[[0, 3)]-{0}-[2] --> $s0
Variable_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	jal	Expr_init
	move	$a0, $s0
	j	__Variable_init_epilogue
__Variable_init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 1
# VR0-[[0, 3)]-{0}-[2] --> $s0
Lambda_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	jal	Expr_init
	move	$a0, $s0
	j	__Lambda_init_epilogue
__Lambda_init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 1
# VR0-[[0, 3)]-{0}-[2] --> $s0
App_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	jal	Expr_init
	move	$a0, $s0
	j	__App_init_epilogue
__App_init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 1
# VR0-[[0, 3)]-{0}-[2] --> $s0
VarListNE_init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	jal	VarList_init
	move	$a0, $s0
	j	__VarListNE_init_epilogue
__VarListNE_init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 2
# VR0-[[0, 1)]-{0}-[] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s0
LambdaList.isNil:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	li	$s0, 1
	move	$a0, $s0
	j	__LambdaList.isNil_epilogue
__LambdaList.isNil_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 9
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s1
# VR1-[[12, 13)]-{6}-[] --> $s0
# VR1-[[13, 15)]-{7}-[14] --> $s0
# VR1-[[16, 19)]-{8}-[18] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s0
# VR2-[[5, 7)]-{3}-[6] --> $s0
# VR2-[[9, 11)]-{4}-[10] --> $s0
# VR2-[[10, 12)]-{5}-[11] --> $s1
LambdaList.headE:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid0
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 46
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid0:
	move	$a0, $s1
	lw	$s0, 8 ($s1)
	lw	$s1, 0 ($s0)
	jalr	$s1
	move	$s0, $a0
	la	$s0, VarList_protObj
	move	$a0, $s0
	jal	Object.copy
	move	$s0, $a0
	jal	VarList_init
	move	$a0, $s0
	j	__LambdaList.headE_epilogue
__LambdaList.headE_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 9
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s1
# VR1-[[12, 13)]-{6}-[] --> $s0
# VR1-[[13, 15)]-{7}-[14] --> $s0
# VR1-[[16, 19)]-{8}-[18] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s0
# VR2-[[5, 7)]-{3}-[6] --> $s0
# VR2-[[9, 11)]-{4}-[10] --> $s0
# VR2-[[10, 12)]-{5}-[11] --> $s1
LambdaList.headC:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid1
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 47
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid1:
	move	$a0, $s1
	lw	$s0, 8 ($s1)
	lw	$s1, 0 ($s0)
	jalr	$s1
	move	$s0, $a0
	la	$s0, Lambda_protObj
	move	$a0, $s0
	jal	Object.copy
	move	$s0, $a0
	jal	Lambda_init
	move	$a0, $s0
	j	__LambdaList.headC_epilogue
__LambdaList.headC_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 8
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s1
# VR1-[[12, 13)]-{6}-[] --> $s0
# VR1-[[13, 15)]-{7}-[14] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s0
# VR2-[[5, 7)]-{3}-[6] --> $s0
# VR2-[[9, 11)]-{4}-[10] --> $s0
# VR2-[[10, 12)]-{5}-[11] --> $s1
LambdaList.headN:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid2
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 48
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid2:
	move	$a0, $s1
	lw	$s0, 8 ($s1)
	lw	$s1, 0 ($s0)
	jalr	$s1
	move	$s0, $a0
	li	$s0, 0
	move	$a0, $s0
	j	__LambdaList.headN_epilogue
__LambdaList.headN_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 9
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s1
# VR1-[[12, 13)]-{6}-[] --> $s0
# VR1-[[13, 15)]-{7}-[14] --> $s0
# VR1-[[16, 19)]-{8}-[18] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s0
# VR2-[[5, 7)]-{3}-[6] --> $s0
# VR2-[[9, 11)]-{4}-[10] --> $s0
# VR2-[[10, 12)]-{5}-[11] --> $s1
LambdaList.tail:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid3
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 49
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid3:
	move	$a0, $s1
	lw	$s0, 8 ($s1)
	lw	$s1, 0 ($s0)
	jalr	$s1
	move	$s0, $a0
	la	$s0, LambdaList_protObj
	move	$a0, $s0
	jal	Object.copy
	move	$s0, $a0
	jal	LambdaList_init
	move	$a0, $s0
	j	__LambdaList.tail_epilogue
__LambdaList.tail_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 15
# VR0-[[0, 10), [10, 15), [15, 19)]-{0}-[18] --> $s0
# VR1-[[1, 10), [10, 15), [15, 16)]-{1}-[15] --> $s1
# VR2-[[2, 10), [10, 15), [15, 17)]-{2}-[16] --> $s2
# VR3-[[3, 10), [10, 15), [15, 18)]-{3}-[17] --> $s3
# VR4-[[4, 6)]-{4}-[5] --> $s4
# VR4-[[7, 10), [10, 15), [15, 25)]-{5}-[19, 9, 24] --> $s4
# VR4-[[27, 29)]-{14}-[28] --> $s0
# VR5-[[10, 12)]-{6}-[11] --> $s5
# VR5-[[12, 14)]-{7}-[13] --> $s5
# VR5-[[15, 21)]-{8}-[20] --> $s5
# VR5-[[24, 26)]-{12}-[25] --> $s0
# VR5-[[25, 27)]-{13}-[26] --> $s1
# VR6-[[16, 22)]-{9}-[21] --> $s1
# VR7-[[17, 23)]-{10}-[22] --> $s2
# VR8-[[18, 24)]-{11}-[23] --> $s3
LambdaList.add:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 16 ($fp)
	lw	$s2, 12 ($fp)
	lw	$s3, 8 ($fp)
	la	$s4, LambdaListNE_protObj
	move	$a0, $s4
	jal	Object.copy
	move	$s4, $a0
	jal	LambdaListNE_init
	bnez	$s4, dispatch_notvoid4
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 51
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid4:
	move	$s5, $s1
	move	$s1, $s2
	move	$s2, $s3
	move	$s3, $s0
	move	$a0, $s4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s4)
	lw	$s1, 36 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__LambdaList.add_epilogue
__LambdaList.add_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s5, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 20
	jr	$ra

# web count: 7
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s1
# VR1-[[12, 14)]-{6}-[13] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s0
# VR2-[[5, 7)]-{3}-[6] --> $s0
# VR2-[[9, 11)]-{4}-[10] --> $s0
# VR2-[[10, 12)]-{5}-[11] --> $s1
LambdaListRef.isNil:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 16 ($s0)
	bnez	$s1, dispatch_notvoid5
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 79
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid5:
	move	$a0, $s1
	lw	$s0, 8 ($s1)
	lw	$s1, 12 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__LambdaListRef.isNil_epilogue
__LambdaListRef.isNil_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 7
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s1
# VR1-[[12, 14)]-{6}-[13] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s0
# VR2-[[5, 7)]-{3}-[6] --> $s0
# VR2-[[9, 11)]-{4}-[10] --> $s0
# VR2-[[10, 12)]-{5}-[11] --> $s1
LambdaListRef.headE:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 16 ($s0)
	bnez	$s1, dispatch_notvoid6
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 80
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid6:
	move	$a0, $s1
	lw	$s0, 8 ($s1)
	lw	$s1, 16 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__LambdaListRef.headE_epilogue
__LambdaListRef.headE_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 7
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s1
# VR1-[[12, 14)]-{6}-[13] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s0
# VR2-[[5, 7)]-{3}-[6] --> $s0
# VR2-[[9, 11)]-{4}-[10] --> $s0
# VR2-[[10, 12)]-{5}-[11] --> $s1
LambdaListRef.headC:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 16 ($s0)
	bnez	$s1, dispatch_notvoid7
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 81
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid7:
	move	$a0, $s1
	lw	$s0, 8 ($s1)
	lw	$s1, 20 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__LambdaListRef.headC_epilogue
__LambdaListRef.headC_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 7
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s1
# VR1-[[12, 14)]-{6}-[13] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s0
# VR2-[[5, 7)]-{3}-[6] --> $s0
# VR2-[[9, 11)]-{4}-[10] --> $s0
# VR2-[[10, 12)]-{5}-[11] --> $s1
LambdaListRef.headN:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 16 ($s0)
	bnez	$s1, dispatch_notvoid8
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 82
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid8:
	move	$a0, $s1
	lw	$s0, 8 ($s1)
	lw	$s1, 24 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__LambdaListRef.headN_epilogue
__LambdaListRef.headN_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 5
# VR0-[[0, 10)]-{0}-[2, 8, 9] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s1
# VR1-[[3, 5)]-{2}-[4] --> $s1
# VR1-[[6, 9)]-{3}-[8] --> $s1
# VR1-[[9, 11)]-{4}-[10] --> $s1
LambdaListRef.reset:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	li	$s1, 0
	sw	$s1, 12 ($s0)
	la	$s1, LambdaList_protObj
	move	$a0, $s1
	jal	Object.copy
	move	$s1, $a0
	jal	LambdaList_init
	sw	$s1, 16 ($s0)
	move	$s1, $s0
	move	$a0, $s1
	j	__LambdaListRef.reset_epilogue
__LambdaListRef.reset_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 18
# VR0-[[0, 5), [5, 10), [10, 27)]-{0}-[3, 21, 22, 25, 26, 12] --> $s0
# VR1-[[1, 5), [5, 10), [10, 11)]-{1}-[10] --> $s1
# VR2-[[2, 5), [5, 10), [10, 12)]-{2}-[11] --> $s2
# VR3-[[3, 5), [5, 10), [10, 18)]-{3}-[17, 4, 13] --> $s3
# VR3-[[20, 22)]-{11}-[21] --> $s1
# VR3-[[22, 25)]-{12}-[24] --> $s1
# VR3-[[24, 26)]-{14}-[25] --> $s2
# VR3-[[26, 29)]-{15}-[28] --> $s1
# VR3-[[28, 30)]-{17}-[29] --> $s0
# VR4-[[5, 7)]-{4}-[6] --> $s4
# VR4-[[7, 9)]-{5}-[8] --> $s4
# VR4-[[10, 15)]-{6}-[14] --> $s4
# VR4-[[17, 19)]-{9}-[18] --> $s1
# VR4-[[18, 20)]-{10}-[19] --> $s2
# VR4-[[23, 25)]-{13}-[24] --> $s3
# VR4-[[27, 29)]-{16}-[28] --> $s2
# VR5-[[11, 16)]-{7}-[15] --> $s1
# VR6-[[12, 17)]-{8}-[16] --> $s2
LambdaListRef.add:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($fp)
	lw	$s2, 8 ($fp)
	lw	$s3, 16 ($s0)
	bnez	$s3, dispatch_notvoid9
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 92
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid9:
	move	$s4, $s1
	move	$s1, $s2
	lw	$s2, 12 ($s0)
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s3)
	lw	$s2, 32 ($s1)
	jalr	$s2
	move	$s1, $a0
	sw	$s1, 16 ($s0)
	lw	$s1, 12 ($s0)
	li	$s3, 1
	add	$s2, $s1, $s3
	sw	$s2, 12 ($s0)
	lw	$s1, 12 ($s0)
	li	$s2, 1
	sub	$s0, $s1, $s2
	move	$a0, $s0
	j	__LambdaListRef.add_epilogue
__LambdaListRef.add_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 8
# VR0-[[0, 3), [3, 8), [8, 15)]-{0}-[1, 13, 14] --> $s0
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s1
# VR1-[[12, 14)]-{6}-[13] --> $s1
# VR1-[[14, 16)]-{7}-[15] --> $s1
# VR2-[[3, 5)]-{2}-[4] --> $s2
# VR2-[[5, 7)]-{3}-[6] --> $s2
# VR2-[[9, 11)]-{4}-[10] --> $s2
# VR2-[[10, 12)]-{5}-[11] --> $s1
LambdaListRef.removeHead:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 16 ($s0)
	bnez	$s1, dispatch_notvoid10
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 99
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid10:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 28 ($s2)
	jalr	$s1
	move	$s1, $a0
	sw	$s1, 16 ($s0)
	move	$s1, $s0
	move	$a0, $s1
	j	__LambdaListRef.removeHead_epilogue
__LambdaListRef.removeHead_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 2
# VR0-[[0, 1)]-{0}-[] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s0
LambdaListNE.isNil:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	li	$s0, 0
	move	$a0, $s0
	j	__LambdaListNE.isNil_epilogue
__LambdaListNE.isNil_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 2
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s1
LambdaListNE.headE:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 20 ($s0)
	move	$a0, $s1
	j	__LambdaListNE.headE_epilogue
__LambdaListNE.headE_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 2
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s1
LambdaListNE.headC:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($s0)
	move	$a0, $s1
	j	__LambdaListNE.headC_epilogue
__LambdaListNE.headC_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 2
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s1
LambdaListNE.headN:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 16 ($s0)
	move	$a0, $s1
	j	__LambdaListNE.headN_epilogue
__LambdaListNE.headN_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 2
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s1
LambdaListNE.tail:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 24 ($s0)
	move	$a0, $s1
	j	__LambdaListNE.tail_epilogue
__LambdaListNE.tail_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 10
# VR0-[[0, 14)]-{0}-[6, 8, 10, 12, 13] --> $s0
# VR1-[[1, 6)]-{1}-[5] --> $s1
# VR2-[[2, 8)]-{2}-[7] --> $s2
# VR3-[[3, 10)]-{3}-[9] --> $s3
# VR4-[[4, 12)]-{4}-[11] --> $s4
# VR5-[[5, 7)]-{5}-[6] --> $s5
# VR5-[[7, 9)]-{6}-[8] --> $s1
# VR5-[[9, 11)]-{7}-[10] --> $s1
# VR5-[[11, 13)]-{8}-[12] --> $s1
# VR5-[[13, 15)]-{9}-[14] --> $s1
LambdaListNE.init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 20 ($fp)
	lw	$s2, 16 ($fp)
	lw	$s3, 12 ($fp)
	lw	$s4, 8 ($fp)
	move	$s5, $s1
	sw	$s5, 20 ($s0)
	move	$s1, $s2
	sw	$s1, 12 ($s0)
	move	$s1, $s3
	sw	$s1, 16 ($s0)
	move	$s1, $s4
	sw	$s1, 24 ($s0)
	move	$s1, $s0
	move	$a0, $s1
	j	__LambdaListNE.init_epilogue
__LambdaListNE.init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s5, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 24
	jr	$ra

# web count: 2
# VR0-[[0, 1)]-{0}-[] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s0
VarList.isNil:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	li	$s0, 1
	move	$a0, $s0
	j	__VarList.isNil_epilogue
__VarList.isNil_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 9
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s1
# VR1-[[12, 13)]-{6}-[] --> $s0
# VR1-[[13, 15)]-{7}-[14] --> $s0
# VR1-[[16, 19)]-{8}-[18] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s0
# VR2-[[5, 7)]-{3}-[6] --> $s0
# VR2-[[9, 11)]-{4}-[10] --> $s0
# VR2-[[10, 12)]-{5}-[11] --> $s1
VarList.head:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid11
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 23
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid11:
	move	$a0, $s1
	lw	$s0, 8 ($s1)
	lw	$s1, 0 ($s0)
	jalr	$s1
	move	$s0, $a0
	la	$s0, Variable_protObj
	move	$a0, $s0
	jal	Object.copy
	move	$s0, $a0
	jal	Variable_init
	move	$a0, $s0
	j	__VarList.head_epilogue
__VarList.head_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 9
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s1
# VR1-[[12, 13)]-{6}-[] --> $s0
# VR1-[[13, 15)]-{7}-[14] --> $s0
# VR1-[[16, 19)]-{8}-[18] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s0
# VR2-[[5, 7)]-{3}-[6] --> $s0
# VR2-[[9, 11)]-{4}-[10] --> $s0
# VR2-[[10, 12)]-{5}-[11] --> $s1
VarList.tail:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid12
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 24
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid12:
	move	$a0, $s1
	lw	$s0, 8 ($s1)
	lw	$s1, 0 ($s0)
	jalr	$s1
	move	$s0, $a0
	la	$s0, VarList_protObj
	move	$a0, $s0
	jal	Object.copy
	move	$s0, $a0
	jal	VarList_init
	move	$a0, $s0
	j	__VarList.tail_epilogue
__VarList.tail_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 11
# VR0-[[0, 8), [8, 13), [13, 15)]-{0}-[14] --> $s0
# VR1-[[1, 8), [8, 13), [13, 14)]-{1}-[13] --> $s1
# VR2-[[2, 4)]-{2}-[3] --> $s2
# VR2-[[5, 8), [8, 13), [13, 19)]-{3}-[18, 7, 15] --> $s2
# VR2-[[21, 23)]-{10}-[22] --> $s0
# VR3-[[8, 10)]-{4}-[9] --> $s3
# VR3-[[10, 12)]-{5}-[11] --> $s3
# VR3-[[13, 17)]-{6}-[16] --> $s3
# VR3-[[18, 20)]-{8}-[19] --> $s0
# VR3-[[19, 21)]-{9}-[20] --> $s1
# VR4-[[14, 18)]-{7}-[17] --> $s1
VarList.add:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 8 ($fp)
	la	$s2, VarListNE_protObj
	move	$a0, $s2
	jal	Object.copy
	move	$s2, $a0
	jal	VarListNE_init
	bnez	$s2, dispatch_notvoid13
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 25
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid13:
	move	$s3, $s1
	move	$s1, $s0
	move	$a0, $s2
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s2)
	lw	$s1, 48 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__VarList.add_epilogue
__VarList.add_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 12
	jr	$ra

# web count: 8
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3), [3, 8), [8, 12)]-{1}-[2, 9, 11] --> $s1
# VR1-[[14, 16)]-{7}-[15] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s0
# VR2-[[5, 7)]-{3}-[6] --> $s0
# VR2-[[8, 11)]-{4}-[10] --> $s0
# VR2-[[11, 13)]-{5}-[12] --> $s0
# VR2-[[12, 14)]-{6}-[13] --> $s1
VarList.print:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid14
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 26
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid14:
	la	$s0, str_const1
	move	$a0, $s1
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s1)
	lw	$s1, 12 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__VarList.print_epilogue
__VarList.print_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 15
# VR0-[[0, 3), [3, 8), [8, 17), [17, 22), [22, 28)]-{0}-[1, 27, 15] --> $s0
# VR1-[[1, 3), [3, 8), [8, 12)]-{1}-[2, 9, 11] --> $s1
# VR1-[[14, 15)]-{7}-[] --> $s1
# VR1-[[15, 17), [17, 22), [22, 24)]-{8}-[16, 23, 22] --> $s1
# VR1-[[26, 27)]-{13}-[] --> $s1
# VR1-[[27, 29)]-{14}-[28] --> $s1
# VR2-[[3, 5)]-{2}-[4] --> $s2
# VR2-[[5, 7)]-{3}-[6] --> $s2
# VR2-[[8, 11)]-{4}-[10] --> $s2
# VR2-[[11, 13)]-{5}-[12] --> $s2
# VR2-[[12, 14)]-{6}-[13] --> $s1
# VR2-[[17, 19)]-{9}-[18] --> $s2
# VR2-[[19, 21)]-{10}-[20] --> $s2
# VR2-[[23, 25)]-{11}-[24] --> $s2
# VR2-[[24, 26)]-{12}-[25] --> $s1
Expr.print_self:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid15
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 116
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid15:
	la	$s2, str_const3
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid16
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 117
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid16:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 0 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	move	$a0, $s1
	j	__Expr.print_self_epilogue
__Expr.print_self_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 15
# VR0-[[0, 3), [3, 8), [8, 17), [17, 22), [22, 28)]-{0}-[1, 27, 15] --> $s0
# VR1-[[1, 3), [3, 8), [8, 12)]-{1}-[2, 9, 11] --> $s1
# VR1-[[14, 15)]-{7}-[] --> $s1
# VR1-[[15, 17), [17, 22), [22, 24)]-{8}-[16, 23, 22] --> $s1
# VR1-[[26, 27)]-{13}-[] --> $s1
# VR1-[[27, 29)]-{14}-[28] --> $s1
# VR2-[[3, 5)]-{2}-[4] --> $s2
# VR2-[[5, 7)]-{3}-[6] --> $s2
# VR2-[[8, 11)]-{4}-[10] --> $s2
# VR2-[[11, 13)]-{5}-[12] --> $s2
# VR2-[[12, 14)]-{6}-[13] --> $s1
# VR2-[[17, 19)]-{9}-[18] --> $s2
# VR2-[[19, 21)]-{10}-[20] --> $s2
# VR2-[[23, 25)]-{11}-[24] --> $s2
# VR2-[[24, 26)]-{12}-[25] --> $s1
Expr.beta:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid17
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 125
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid17:
	la	$s2, str_const4
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid18
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 126
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid18:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 0 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	move	$a0, $s1
	j	__Expr.beta_epilogue
__Expr.beta_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 17
# VR0-[[0, 5), [5, 10), [10, 19), [19, 24), [24, 30)]-{0}-[17, 3, 29] --> $s0
# VR1-[[1, 2)]-{1}-[] --> $s1
# VR2-[[2, 3)]-{2}-[] --> $s1
# VR3-[[3, 5), [5, 10), [10, 14)]-{3}-[4, 11, 13] --> $s1
# VR3-[[16, 17)]-{9}-[] --> $s1
# VR3-[[17, 19), [19, 24), [24, 26)]-{10}-[18, 25, 24] --> $s1
# VR3-[[28, 29)]-{15}-[] --> $s1
# VR3-[[29, 31)]-{16}-[30] --> $s1
# VR4-[[5, 7)]-{4}-[6] --> $s2
# VR4-[[7, 9)]-{5}-[8] --> $s2
# VR4-[[10, 13)]-{6}-[12] --> $s2
# VR4-[[13, 15)]-{7}-[14] --> $s2
# VR4-[[14, 16)]-{8}-[15] --> $s1
# VR4-[[19, 21)]-{11}-[20] --> $s2
# VR4-[[21, 23)]-{12}-[22] --> $s2
# VR4-[[25, 27)]-{13}-[26] --> $s2
# VR4-[[26, 28)]-{14}-[27] --> $s1
Expr.substitute:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($fp)
	lw	$s1, 8 ($fp)
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid19
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 134
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid19:
	la	$s2, str_const5
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid20
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 135
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid20:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 0 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	move	$a0, $s1
	j	__Expr.substitute_epilogue
__Expr.substitute_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 17
# VR0-[[0, 5), [5, 10), [10, 19), [19, 24), [24, 30)]-{0}-[17, 3, 29] --> $s0
# VR1-[[1, 2)]-{1}-[] --> $s1
# VR2-[[2, 3)]-{2}-[] --> $s1
# VR3-[[3, 5), [5, 10), [10, 14)]-{3}-[4, 11, 13] --> $s1
# VR3-[[16, 17)]-{9}-[] --> $s1
# VR3-[[17, 19), [19, 24), [24, 26)]-{10}-[18, 25, 24] --> $s1
# VR3-[[28, 29)]-{15}-[] --> $s1
# VR3-[[29, 31)]-{16}-[30] --> $s1
# VR4-[[5, 7)]-{4}-[6] --> $s2
# VR4-[[7, 9)]-{5}-[8] --> $s2
# VR4-[[10, 13)]-{6}-[12] --> $s2
# VR4-[[13, 15)]-{7}-[14] --> $s2
# VR4-[[14, 16)]-{8}-[15] --> $s1
# VR4-[[19, 21)]-{11}-[20] --> $s2
# VR4-[[21, 23)]-{12}-[22] --> $s2
# VR4-[[25, 27)]-{13}-[26] --> $s2
# VR4-[[26, 28)]-{14}-[27] --> $s1
Expr.gen_code:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($fp)
	lw	$s1, 8 ($fp)
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid21
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 143
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid21:
	la	$s2, str_const6
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid22
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 144
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid22:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 0 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	move	$a0, $s1
	j	__Expr.gen_code_epilogue
__Expr.gen_code_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 12
# VR0-[[0, 1)]-{0}-[] --> $s0
# VR1-[[1, 9), [9, 14), [14, 15)]-{1}-[14] --> $s0
# VR2-[[2, 4)]-{2}-[3] --> $s1
# VR2-[[5, 8)]-{3}-[7] --> $s1
# VR2-[[21, 23)]-{11}-[22] --> $s0
# VR3-[[7, 9), [9, 14), [14, 18)]-{4}-[17, 8, 15] --> $s2
# VR3-[[20, 22)]-{10}-[21] --> $s1
# VR4-[[9, 11)]-{5}-[10] --> $s1
# VR4-[[11, 13)]-{6}-[12] --> $s1
# VR4-[[14, 17)]-{7}-[16] --> $s1
# VR4-[[17, 19)]-{8}-[18] --> $s0
# VR4-[[18, 20)]-{9}-[19] --> $s1
Term.var:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s0, 8 ($fp)
	la	$s1, Variable_protObj
	move	$a0, $s1
	jal	Object.copy
	move	$s1, $a0
	jal	Variable_init
	move	$s2, $s1
	bnez	$s2, dispatch_notvoid23
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 341
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid23:
	move	$s1, $s0
	move	$a0, $s2
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s2)
	lw	$s1, 44 ($s0)
	jalr	$s1
	move	$s1, $a0
	move	$s0, $s1
	move	$a0, $s0
	j	__Term.var_epilogue
__Term.var_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 12
	jr	$ra

# web count: 14
# VR0-[[0, 1)]-{0}-[] --> $s0
# VR1-[[1, 10), [10, 15), [15, 16)]-{1}-[15] --> $s0
# VR2-[[2, 10), [10, 15), [15, 17)]-{2}-[16] --> $s1
# VR3-[[3, 5)]-{3}-[4] --> $s2
# VR3-[[6, 9)]-{4}-[8] --> $s2
# VR3-[[24, 26)]-{13}-[25] --> $s0
# VR4-[[8, 10), [10, 15), [15, 21)]-{5}-[17, 20, 9] --> $s3
# VR4-[[23, 25)]-{12}-[24] --> $s1
# VR5-[[10, 12)]-{6}-[11] --> $s2
# VR5-[[12, 14)]-{7}-[13] --> $s2
# VR5-[[15, 19)]-{8}-[18] --> $s2
# VR5-[[20, 22)]-{10}-[21] --> $s0
# VR5-[[21, 23)]-{11}-[22] --> $s1
# VR6-[[16, 20)]-{9}-[19] --> $s0
Term.lam:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s0, 12 ($fp)
	lw	$s1, 8 ($fp)
	la	$s2, Lambda_protObj
	move	$a0, $s2
	jal	Object.copy
	move	$s2, $a0
	jal	Lambda_init
	move	$s3, $s2
	bnez	$s3, dispatch_notvoid24
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 346
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid24:
	move	$s2, $s0
	move	$s0, $s1
	move	$a0, $s3
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s3)
	lw	$s1, 44 ($s0)
	jalr	$s1
	move	$s1, $a0
	move	$s0, $s1
	move	$a0, $s0
	j	__Term.lam_epilogue
__Term.lam_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 14
# VR0-[[0, 1)]-{0}-[] --> $s0
# VR1-[[1, 10), [10, 15), [15, 16)]-{1}-[15] --> $s0
# VR2-[[2, 10), [10, 15), [15, 17)]-{2}-[16] --> $s1
# VR3-[[3, 5)]-{3}-[4] --> $s2
# VR3-[[6, 9)]-{4}-[8] --> $s2
# VR3-[[24, 26)]-{13}-[25] --> $s0
# VR4-[[8, 10), [10, 15), [15, 21)]-{5}-[17, 20, 9] --> $s3
# VR4-[[23, 25)]-{12}-[24] --> $s1
# VR5-[[10, 12)]-{6}-[11] --> $s2
# VR5-[[12, 14)]-{7}-[13] --> $s2
# VR5-[[15, 19)]-{8}-[18] --> $s2
# VR5-[[20, 22)]-{10}-[21] --> $s0
# VR5-[[21, 23)]-{11}-[22] --> $s1
# VR6-[[16, 20)]-{9}-[19] --> $s0
Term.app:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s0, 12 ($fp)
	lw	$s1, 8 ($fp)
	la	$s2, App_protObj
	move	$a0, $s2
	jal	Object.copy
	move	$s2, $a0
	jal	App_init
	move	$s3, $s2
	bnez	$s3, dispatch_notvoid25
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 351
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid25:
	move	$s2, $s0
	move	$s0, $s1
	move	$a0, $s3
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s3)
	lw	$s1, 44 ($s0)
	jalr	$s1
	move	$s1, $a0
	move	$s0, $s1
	move	$a0, $s0
	j	__Term.app_epilogue
__Term.app_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 17
# VR0-[[0, 3), [3, 8), [8, 16)]-{0}-[1, 15] --> $s0
# VR1-[[1, 3), [3, 8), [8, 12)]-{1}-[2, 9, 11] --> $s1
# VR1-[[14, 17), [17, 22), [22, 24)]-{7}-[23, 22] --> $s1
# VR1-[[31, 33)]-{16}-[32] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s2
# VR2-[[5, 7)]-{3}-[6] --> $s2
# VR2-[[8, 11)]-{4}-[10] --> $s2
# VR2-[[11, 13)]-{5}-[12] --> $s2
# VR2-[[12, 14)]-{6}-[13] --> $s1
# VR2-[[15, 17), [17, 22), [22, 28)]-{8}-[16, 24, 27] --> $s2
# VR2-[[30, 32)]-{15}-[31] --> $s1
# VR3-[[17, 19)]-{9}-[18] --> $s0
# VR3-[[19, 21)]-{10}-[20] --> $s0
# VR3-[[22, 26)]-{11}-[25] --> $s0
# VR3-[[27, 29)]-{13}-[28] --> $s0
# VR3-[[28, 30)]-{14}-[29] --> $s1
# VR4-[[23, 27)]-{12}-[26] --> $s3
Term.i:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid26
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 358
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid26:
	la	$s2, str_const35
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 28 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s2, $s0
	bnez	$s2, dispatch_notvoid27
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 359
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid27:
	move	$s0, $s1
	move	$s3, $s1
	move	$a0, $s2
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s2)
	lw	$s1, 32 ($s0)
	jalr	$s1
	move	$s1, $a0
	move	$s0, $s1
	move	$a0, $s0
	j	__Term.i_epilogue
__Term.i_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 32
# VR0-[[0, 3), [3, 8), [8, 17), [17, 22), [22, 31), [31, 36), [36, 38)]-{0}-[1, 37, 29, 15] --> $s0
# VR1-[[1, 3), [3, 8), [8, 12)]-{1}-[2, 9, 11] --> $s1
# VR1-[[14, 17), [17, 22), [22, 31), [31, 36), [36, 39), [39, 44), [44, 46)]-{7}-[36, 45] --> $s1
# VR1-[[61, 63)]-{31}-[62] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s2
# VR2-[[5, 7)]-{3}-[6] --> $s2
# VR2-[[8, 11)]-{4}-[10] --> $s2
# VR2-[[11, 13)]-{5}-[12] --> $s2
# VR2-[[12, 14)]-{6}-[13] --> $s1
# VR2-[[15, 17), [17, 22), [22, 26)]-{8}-[16, 23, 25] --> $s2
# VR2-[[28, 31), [31, 36), [36, 39), [39, 44), [44, 45)]-{14}-[44] --> $s2
# VR2-[[60, 62)]-{30}-[61] --> $s1
# VR3-[[17, 19)]-{9}-[18] --> $s3
# VR3-[[19, 21)]-{10}-[20] --> $s3
# VR3-[[22, 25)]-{11}-[24] --> $s3
# VR3-[[25, 27)]-{12}-[26] --> $s3
# VR3-[[26, 28)]-{13}-[27] --> $s2
# VR3-[[29, 31), [31, 36), [36, 39), [39, 44), [44, 57)]-{15}-[53, 56, 30] --> $s3
# VR3-[[59, 61)]-{29}-[60] --> $s0
# VR4-[[31, 33)]-{16}-[32] --> $s4
# VR4-[[33, 35)]-{17}-[34] --> $s4
# VR4-[[36, 39), [39, 44), [44, 55)]-{18}-[54] --> $s4
# VR4-[[56, 58)]-{27}-[57] --> $s0
# VR4-[[57, 59)]-{28}-[58] --> $s1
# VR5-[[37, 39), [39, 44), [44, 50)]-{19}-[49, 38, 46] --> $s5
# VR5-[[52, 56)]-{26}-[55] --> $s0
# VR6-[[39, 41)]-{20}-[40] --> $s0
# VR6-[[41, 43)]-{21}-[42] --> $s0
# VR6-[[44, 48)]-{22}-[47] --> $s0
# VR6-[[49, 51)]-{24}-[50] --> $s0
# VR6-[[50, 52)]-{25}-[51] --> $s1
# VR7-[[45, 49)]-{23}-[48] --> $s2
Term.k:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid28
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 363
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid28:
	la	$s2, str_const35
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 28 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s2, $s0
	bnez	$s2, dispatch_notvoid29
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 364
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid29:
	la	$s3, str_const36
	move	$a0, $s2
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s3, 8 ($s2)
	lw	$s2, 28 ($s3)
	jalr	$s2
	move	$s2, $a0
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid30
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 365
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid30:
	move	$s4, $s1
	move	$s5, $s0
	bnez	$s5, dispatch_notvoid31
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 365
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid31:
	move	$s0, $s2
	move	$s2, $s1
	move	$a0, $s5
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s5)
	lw	$s1, 32 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s3)
	lw	$s1, 32 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$s1, $s0
	move	$s0, $s1
	move	$a0, $s0
	j	__Term.k_epilogue
__Term.k_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s5, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 68
# VR0-[[0, 3), [3, 8), [8, 17), [17, 22), [22, 31), [31, 36), [36, 45), [45, 50), [50, 53), [53, 58), [58, 61), [61, 66), [66, 69), [69, 74), [74, 76), [76, 81), [81, 91)]-{0}-[51, 1, 67, 59, 43, 29, 74, 15, 90] spilled
# VR1-[[1, 3), [3, 8), [8, 12)]-{1}-[2, 9, 11] --> $s0
# VR1-[[14, 17), [17, 22), [22, 31), [31, 36), [36, 45), [45, 50), [50, 53), [53, 58), [58, 61), [61, 66), [66, 69), [69, 74), [74, 76), [76, 81), [81, 82)]-{7}-[50, 81] spilled
# VR1-[[136, 138)]-{67}-[137] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s1
# VR2-[[5, 7)]-{3}-[6] --> $s1
# VR2-[[8, 11)]-{4}-[10] --> $s1
# VR2-[[11, 13)]-{5}-[12] --> $s1
# VR2-[[12, 14)]-{6}-[13] --> $s0
# VR2-[[15, 17), [17, 22), [22, 26)]-{8}-[16, 23, 25] --> $s0
# VR2-[[28, 31), [31, 36), [36, 45), [45, 50), [50, 53), [53, 58), [58, 61), [61, 66), [66, 69), [69, 74), [74, 76), [76, 81), [81, 92), [92, 97), [97, 98)]-{14}-[97, 58] spilled
# VR2-[[135, 137)]-{66}-[136] --> $s1
# VR3-[[17, 19)]-{9}-[18] --> $s1
# VR3-[[19, 21)]-{10}-[20] --> $s1
# VR3-[[22, 25)]-{11}-[24] --> $s1
# VR3-[[25, 27)]-{12}-[26] --> $s1
# VR3-[[26, 28)]-{13}-[27] --> $s0
# VR3-[[29, 31), [31, 36), [36, 40)]-{15}-[39, 37, 30] --> $s0
# VR3-[[42, 45), [45, 50), [50, 53), [53, 58), [58, 61), [61, 66), [66, 69), [69, 74), [74, 76), [76, 81), [81, 92), [92, 97), [97, 99)]-{21}-[98, 66, 82] --> $s0
# VR3-[[134, 136)]-{65}-[135] --> $s0
# VR4-[[31, 33)]-{16}-[32] --> $s1
# VR4-[[33, 35)]-{17}-[34] --> $s1
# VR4-[[36, 39)]-{18}-[38] --> $s1
# VR4-[[39, 41)]-{19}-[40] --> $s1
# VR4-[[40, 42)]-{20}-[41] --> $s0
# VR4-[[43, 45), [45, 50), [50, 53), [53, 58), [58, 61), [61, 66), [66, 69), [69, 74), [74, 76), [76, 81), [81, 92), [92, 97), [97, 131)]-{22}-[127, 130, 44] spilled
# VR4-[[133, 135)]-{64}-[134] --> $s1
# VR5-[[45, 47)]-{23}-[46] --> $s1
# VR5-[[47, 49)]-{24}-[48] --> $s1
# VR5-[[50, 53), [53, 58), [58, 61), [61, 66), [66, 69), [69, 74), [74, 76), [76, 81), [81, 92), [92, 97), [97, 129)]-{25}-[128] spilled
# VR5-[[130, 132)]-{62}-[131] --> $s0
# VR5-[[131, 133)]-{63}-[132] --> $s1
# VR6-[[51, 53), [53, 58), [58, 61), [61, 66), [66, 69), [69, 74), [74, 76), [76, 81), [81, 92), [92, 97), [97, 124)]-{26}-[52, 123, 120] spilled
# VR6-[[126, 130)]-{61}-[129] --> $s0
# VR7-[[53, 55)]-{27}-[54] --> $s1
# VR7-[[55, 57)]-{28}-[56] --> $s1
# VR7-[[58, 61), [61, 66), [66, 69), [69, 74), [74, 76), [76, 81), [81, 92), [92, 97), [97, 122)]-{29}-[121] spilled
# VR7-[[123, 125)]-{59}-[124] --> $s0
# VR7-[[124, 126)]-{60}-[125] --> $s1
# VR8-[[59, 61), [61, 66), [66, 69), [69, 74), [74, 76), [76, 81), [81, 92), [92, 97), [97, 117)]-{30}-[116, 113, 60] spilled
# VR8-[[119, 123)]-{58}-[122] --> $s0
# VR9-[[61, 63)]-{31}-[62] --> $s1
# VR9-[[63, 65)]-{32}-[64] --> $s1
# VR9-[[66, 69), [69, 74), [74, 76), [76, 81), [81, 92), [92, 97), [97, 115)]-{33}-[114] --> $s1
# VR9-[[116, 118)]-{56}-[117] --> $s0
# VR9-[[117, 119)]-{57}-[118] --> $s1
# VR10-[[67, 69), [69, 74), [74, 76), [76, 81), [81, 92), [92, 97), [97, 110)]-{34}-[68, 109, 106] --> $s2
# VR10-[[112, 116)]-{55}-[115] --> $s0
# VR11-[[69, 71)]-{35}-[70] --> $s3
# VR11-[[71, 73)]-{36}-[72] --> $s3
# VR11-[[74, 76), [76, 81), [81, 87)]-{37}-[86, 83, 75] --> $s3
# VR11-[[89, 92), [92, 97), [97, 108)]-{44}-[107] --> $s3
# VR11-[[109, 111)]-{53}-[110] --> $s0
# VR11-[[110, 112)]-{54}-[111] --> $s2
# VR12-[[76, 78)]-{38}-[77] --> $s4
# VR12-[[78, 80)]-{39}-[79] --> $s4
# VR12-[[81, 85)]-{40}-[84] --> $s4
# VR12-[[86, 88)]-{42}-[87] --> $s4
# VR12-[[87, 89)]-{43}-[88] --> $s3
# VR12-[[90, 92), [92, 97), [97, 103)]-{45}-[102, 99, 91] --> $s4
# VR12-[[105, 109)]-{52}-[108] --> $s0
# VR13-[[82, 86)]-{41}-[85] --> $s5
# VR13-[[92, 94)]-{46}-[93] --> $s5
# VR13-[[94, 96)]-{47}-[95] --> $s5
# VR13-[[97, 101)]-{48}-[100] --> $s5
# VR13-[[102, 104)]-{50}-[103] --> $s0
# VR13-[[103, 105)]-{51}-[104] --> $s4
# VR14-[[98, 102)]-{49}-[101] --> $s6
Term.s:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	addi	 $sp, $sp, -32
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s6, 0 ($sp)
	addi $sp, $sp, -4
	move	$t0, $a0
	sw	$t0, -4 ($fp)
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid32
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 369
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid32:
	la	$s1, str_const35
	move	$a0, $s0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s0)
	lw	$s0, 28 ($s1)
	jalr	$s0
	move	$t0, $a0
	sw	$t0, -8 ($fp)
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid33
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 370
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid33:
	la	$s1, str_const36
	move	$a0, $s0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s0)
	lw	$s0, 28 ($s1)
	jalr	$s0
	move	$t0, $a0
	sw	$t0, -12 ($fp)
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid34
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 371
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid34:
	la	$s1, str_const37
	move	$a0, $s0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s0)
	lw	$s0, 28 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$t0, $t1
	sw	$t0, -16 ($fp)
	lw	$t0, -16 ($fp)
	bnez	$t0, dispatch_notvoid35
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 372
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid35:
	lw	$t1, -8 ($fp)
	move	$t0, $t1
	sw	$t0, -20 ($fp)
	lw	$t1, -4 ($fp)
	move	$t0, $t1
	sw	$t0, -24 ($fp)
	lw	$t0, -24 ($fp)
	bnez	$t0, dispatch_notvoid36
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 372
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid36:
	lw	$t1, -12 ($fp)
	move	$t0, $t1
	sw	$t0, -28 ($fp)
	lw	$t1, -4 ($fp)
	move	$t0, $t1
	sw	$t0, -32 ($fp)
	lw	$t0, -32 ($fp)
	bnez	$t0, dispatch_notvoid37
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 372
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid37:
	move	$s1, $s0
	lw	$t1, -4 ($fp)
	move	$s2, $t1
	bnez	$s2, dispatch_notvoid38
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 372
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid38:
	lw	$t1, -4 ($fp)
	move	$s3, $t1
	bnez	$s3, dispatch_notvoid39
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 372
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid39:
	lw	$t1, -8 ($fp)
	move	$s4, $t1
	move	$s5, $s0
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 36 ($s4)
	jalr	$s3
	move	$s3, $a0
	lw	$t1, -4 ($fp)
	move	$s4, $t1
	bnez	$s4, dispatch_notvoid40
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 372
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid40:
	lw	$t1, -12 ($fp)
	move	$s5, $t1
	move	$s6, $s0
	move	$a0, $s4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s6, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s4)
	lw	$s4, 36 ($s0)
	jalr	$s4
	move	$s0, $a0
	move	$a0, $s2
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s2)
	lw	$s2, 36 ($s0)
	jalr	$s2
	move	$s0, $a0
	lw	$t0, -32 ($fp)
	move	$a0, $t0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$t0, -32 ($fp)
	lw	$s0, 8 ($t0)
	lw	$s1, 32 ($s0)
	jalr	$s1
	move	$s0, $a0
	lw	$t0, -24 ($fp)
	move	$a0, $t0
	lw	$t0, -28 ($fp)
	sw	$t0, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$t0, -24 ($fp)
	lw	$s0, 8 ($t0)
	lw	$s1, 32 ($s0)
	jalr	$s1
	move	$s0, $a0
	lw	$t0, -16 ($fp)
	move	$a0, $t0
	lw	$t0, -20 ($fp)
	sw	$t0, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$t0, -16 ($fp)
	lw	$s0, 8 ($t0)
	lw	$s1, 32 ($s0)
	jalr	$s1
	move	$s1, $a0
	move	$s0, $s1
	move	$s1, $s0
	move	$s0, $s1
	move	$a0, $s0
	j	__Term.s_epilogue
__Term.s_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s6, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s5, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 40
	jr	$ra

# web count: 54
# VR0-[[0, 4), [4, 9), [9, 18), [18, 23), [23, 30), [30, 33), [33, 35), [35, 40), [40, 50), [50, 53), [53, 57), [57, 62), [62, 71), [71, 76), [76, 81), [81, 82), [82, 83)]-{0}-[2, 55, 82] --> $s0
# VR1-[[1, 4), [4, 9), [9, 18), [18, 23), [23, 30), [30, 33), [33, 35), [35, 40), [40, 50), [50, 53), [54, 57), [57, 62), [62, 71), [71, 76), [76, 81), [81, 82), [82, 84), [84, 89), [89, 97)]-{1, 32}-[69, 16, 33, 96, 47] --> $s1
# VR2-[[2, 4), [4, 9), [9, 13)]-{2}-[3, 10, 12] --> $s2
# VR2-[[15, 16)]-{8}-[] --> $s2
# VR2-[[16, 18), [18, 23), [23, 25)]-{9}-[17, 23, 24] --> $s2
# VR2-[[27, 28)]-{14}-[] --> $s2
# VR2-[[28, 30), [30, 33), [33, 35), [35, 40), [40, 50), [51, 53), [53, 57), [57, 62), [62, 71), [71, 76), [76, 81), [81, 82)]-{15, 30}-[30] --> $s2
# VR2-[[98, 100)]-{55}-[99] --> $s0
# VR3-[[4, 6)]-{3}-[5] --> $s3
# VR3-[[6, 8)]-{4}-[7] --> $s3
# VR3-[[9, 12)]-{5}-[11] --> $s3
# VR3-[[12, 14)]-{6}-[13] --> $s3
# VR3-[[13, 15)]-{7}-[14] --> $s2
# VR3-[[18, 20)]-{10}-[19] --> $s3
# VR3-[[20, 22)]-{11}-[21] --> $s3
# VR3-[[24, 26)]-{12}-[25] --> $s3
# VR3-[[25, 27)]-{13}-[26] --> $s2
# VR3-[[29, 30)]-{16}-[] --> $s3
# VR3-[[45, 50), [53, 54)]-{25}-[53, 46] --> $s3
# VR3-[[97, 99)]-{54}-[98] --> $s1
# VR4-[[30, 32)]-{17}-[31] --> $s3
# VR4-[[31, 33)]-{18}-[32] --> $s4
# VR4-[[33, 35), [35, 40), [40, 42)]-{19}-[34, 40, 41] --> $s3
# VR4-[[44, 46)]-{24}-[45] --> $s4
# VR4-[[46, 49)]-{26}-[48] --> $s4
# VR4-[[48, 50)]-{28}-[49] --> $s5
# VR4-[[50, 52)]-{29}-[51] --> $s3
# VR4-[[53, 55)]-{31}-[54] --> $s4
# VR4-[[55, 57), [57, 62), [62, 66)]-{33}-[65, 56, 63] --> $s3
# VR4-[[68, 69)]-{39}-[] --> $s3
# VR4-[[69, 71), [71, 76), [76, 78)]-{40}-[70, 76, 77] --> $s3
# VR4-[[80, 81)]-{45}-[] --> $s3
# VR4-[[82, 84), [84, 89), [89, 93)]-{46}-[83, 92, 90] --> $s2
# VR4-[[95, 96)]-{52}-[] --> $s0
# VR4-[[96, 98)]-{53}-[97] --> $s0
# VR5-[[35, 37)]-{20}-[36] --> $s4
# VR5-[[37, 39)]-{21}-[38] --> $s4
# VR5-[[41, 43)]-{22}-[42] --> $s4
# VR5-[[42, 44)]-{23}-[43] --> $s3
# VR5-[[47, 49)]-{27}-[48] --> $s6
# VR5-[[57, 59)]-{34}-[58] --> $s4
# VR5-[[59, 61)]-{35}-[60] --> $s4
# VR5-[[62, 65)]-{36}-[64] --> $s4
# VR5-[[65, 67)]-{37}-[66] --> $s4
# VR5-[[66, 68)]-{38}-[67] --> $s3
# VR5-[[71, 73)]-{41}-[72] --> $s4
# VR5-[[73, 75)]-{42}-[74] --> $s4
# VR5-[[77, 79)]-{43}-[78] --> $s4
# VR5-[[78, 80)]-{44}-[79] --> $s3
# VR5-[[84, 86)]-{47}-[85] --> $s0
# VR5-[[86, 88)]-{48}-[87] --> $s0
# VR5-[[89, 92)]-{49}-[91] --> $s0
# VR5-[[92, 94)]-{50}-[93] --> $s0
# VR5-[[93, 95)]-{51}-[94] --> $s2
Main.beta_reduce:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s6, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 8 ($fp)
	move	$s2, $s0
	bnez	$s2, dispatch_notvoid41
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 387
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid41:
	la	$s3, str_const38
	move	$a0, $s2
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s3, 8 ($s2)
	lw	$s2, 12 ($s3)
	jalr	$s2
	move	$s2, $a0
	move	$s2, $s1
	bnez	$s2, dispatch_notvoid42
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 388
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid42:
	move	$a0, $s2
	lw	$s3, 8 ($s2)
	lw	$s2, 28 ($s3)
	jalr	$s2
	move	$s2, $a0
	li	$s2, 0
	li	$s3, 0
loop_start0:
	move	$s3, $s2
	li	$t0, 1
	sub	$s4, $t0, $s3
	beqz	$s4, loop_end0
	move	$s3, $s1
	bnez	$s3, dispatch_notvoid43
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 394
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid43:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 32 ($s4)
	jalr	$s3
	move	$s4, $a0
	move	$s3, $s4
	move	$s4, $s3
	move	$s6, $s1
	seq	$s5, $s4, $s6
	beqz	$s5, ite_false0
	li	$s3, 1
	move	$s2, $s3
	b	ite_end0
ite_false0:
	move	$s4, $s3
	move	$s1, $s4
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid44
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 400
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid44:
	la	$s4, str_const39
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 12 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s3, $s1
	bnez	$s3, dispatch_notvoid45
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 401
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid45:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 28 ($s4)
	jalr	$s3
	move	$s3, $a0
ite_end0:
	b	loop_start0
loop_end0:
	move	$s2, $s0
	bnez	$s2, dispatch_notvoid46
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 406
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid46:
	la	$s0, str_const1
	move	$a0, $s2
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s2)
	lw	$s2, 12 ($s0)
	jalr	$s2
	move	$s0, $a0
	move	$s0, $s1
	move	$s1, $s0
	move	$s0, $s1
	move	$a0, $s0
	j	__Main.beta_reduce_epilogue
__Main.beta_reduce_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s6, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s5, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 12
	jr	$ra

# web count: 22
# VR0-[[0, 3), [3, 8), [8, 17), [17, 22), [22, 30)]-{0}-[1, 29, 15] --> $s0
# VR1-[[1, 3), [3, 8), [8, 12)]-{1}-[2, 9, 11] --> $s1
# VR1-[[14, 15)]-{7}-[] --> $s1
# VR1-[[15, 17), [17, 22), [22, 26)]-{8}-[16, 23, 25] --> $s1
# VR1-[[28, 29)]-{14}-[] --> $s1
# VR1-[[29, 31), [31, 36), [36, 40)]-{15}-[39, 37, 30] --> $s1
# VR1-[[42, 44)]-{21}-[43] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s2
# VR2-[[5, 7)]-{3}-[6] --> $s2
# VR2-[[8, 11)]-{4}-[10] --> $s2
# VR2-[[11, 13)]-{5}-[12] --> $s2
# VR2-[[12, 14)]-{6}-[13] --> $s1
# VR2-[[17, 19)]-{9}-[18] --> $s2
# VR2-[[19, 21)]-{10}-[20] --> $s2
# VR2-[[22, 25)]-{11}-[24] --> $s2
# VR2-[[25, 27)]-{12}-[26] --> $s2
# VR2-[[26, 28)]-{13}-[27] --> $s1
# VR2-[[31, 33)]-{16}-[32] --> $s0
# VR2-[[33, 35)]-{17}-[34] --> $s0
# VR2-[[36, 39)]-{18}-[38] --> $s0
# VR2-[[39, 41)]-{19}-[40] --> $s0
# VR2-[[40, 42)]-{20}-[41] --> $s1
Main.eval_class:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid47
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 414
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid47:
	la	$s2, str_const40
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid48
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 415
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid48:
	la	$s2, str_const41
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid49
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 416
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid49:
	la	$s0, str_const23
	move	$a0, $s1
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s1)
	lw	$s1, 12 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__Main.eval_class_epilogue
__Main.eval_class_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 57
# VR0-[[0, 3), [3, 8), [8, 17), [17, 22), [22, 31), [31, 36), [36, 45), [45, 50), [50, 59), [59, 64), [64, 73), [73, 78), [78, 87), [87, 92), [92, 100)]-{0}-[85, 1, 71, 99, 43, 57, 29, 15] --> $s0
# VR1-[[1, 3), [3, 8), [8, 12)]-{1}-[2, 9, 11] --> $s1
# VR1-[[14, 15)]-{7}-[] --> $s1
# VR1-[[15, 17), [17, 22), [22, 26)]-{8}-[16, 23, 25] --> $s1
# VR1-[[28, 29)]-{14}-[] --> $s1
# VR1-[[29, 31), [31, 36), [36, 40)]-{15}-[39, 37, 30] --> $s1
# VR1-[[42, 43)]-{21}-[] --> $s1
# VR1-[[43, 45), [45, 50), [50, 54)]-{22}-[51, 53, 44] --> $s1
# VR1-[[56, 57)]-{28}-[] --> $s1
# VR1-[[57, 59), [59, 64), [64, 68)]-{29}-[65, 67, 58] --> $s1
# VR1-[[70, 71)]-{35}-[] --> $s1
# VR1-[[71, 73), [73, 78), [78, 82)]-{36}-[81, 79, 72] --> $s1
# VR1-[[84, 85)]-{42}-[] --> $s1
# VR1-[[85, 87), [87, 92), [92, 96)]-{43}-[86, 93, 95] --> $s1
# VR1-[[98, 99)]-{49}-[] --> $s1
# VR1-[[99, 101), [101, 106), [106, 110)]-{50}-[100, 109, 107] --> $s1
# VR1-[[112, 114)]-{56}-[113] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s2
# VR2-[[5, 7)]-{3}-[6] --> $s2
# VR2-[[8, 11)]-{4}-[10] --> $s2
# VR2-[[11, 13)]-{5}-[12] --> $s2
# VR2-[[12, 14)]-{6}-[13] --> $s1
# VR2-[[17, 19)]-{9}-[18] --> $s2
# VR2-[[19, 21)]-{10}-[20] --> $s2
# VR2-[[22, 25)]-{11}-[24] --> $s2
# VR2-[[25, 27)]-{12}-[26] --> $s2
# VR2-[[26, 28)]-{13}-[27] --> $s1
# VR2-[[31, 33)]-{16}-[32] --> $s2
# VR2-[[33, 35)]-{17}-[34] --> $s2
# VR2-[[36, 39)]-{18}-[38] --> $s2
# VR2-[[39, 41)]-{19}-[40] --> $s2
# VR2-[[40, 42)]-{20}-[41] --> $s1
# VR2-[[45, 47)]-{23}-[46] --> $s2
# VR2-[[47, 49)]-{24}-[48] --> $s2
# VR2-[[50, 53)]-{25}-[52] --> $s2
# VR2-[[53, 55)]-{26}-[54] --> $s2
# VR2-[[54, 56)]-{27}-[55] --> $s1
# VR2-[[59, 61)]-{30}-[60] --> $s2
# VR2-[[61, 63)]-{31}-[62] --> $s2
# VR2-[[64, 67)]-{32}-[66] --> $s2
# VR2-[[67, 69)]-{33}-[68] --> $s2
# VR2-[[68, 70)]-{34}-[69] --> $s1
# VR2-[[73, 75)]-{37}-[74] --> $s2
# VR2-[[75, 77)]-{38}-[76] --> $s2
# VR2-[[78, 81)]-{39}-[80] --> $s2
# VR2-[[81, 83)]-{40}-[82] --> $s2
# VR2-[[82, 84)]-{41}-[83] --> $s1
# VR2-[[87, 89)]-{44}-[88] --> $s2
# VR2-[[89, 91)]-{45}-[90] --> $s2
# VR2-[[92, 95)]-{46}-[94] --> $s2
# VR2-[[95, 97)]-{47}-[96] --> $s2
# VR2-[[96, 98)]-{48}-[97] --> $s1
# VR2-[[101, 103)]-{51}-[102] --> $s0
# VR2-[[103, 105)]-{52}-[104] --> $s0
# VR2-[[106, 109)]-{53}-[108] --> $s0
# VR2-[[109, 111)]-{54}-[110] --> $s0
# VR2-[[110, 112)]-{55}-[111] --> $s1
Main.closure_class:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid50
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 422
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid50:
	la	$s2, str_const42
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid51
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 423
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid51:
	la	$s2, str_const43
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid52
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 424
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid52:
	la	$s2, str_const44
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid53
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 425
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid53:
	la	$s2, str_const45
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid54
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 426
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid54:
	la	$s2, str_const46
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid55
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 427
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid55:
	la	$s2, str_const47
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid56
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 428
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid56:
	la	$s2, str_const48
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid57
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 429
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid57:
	la	$s0, str_const23
	move	$a0, $s1
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s1)
	lw	$s1, 12 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__Main.closure_class_epilogue
__Main.closure_class_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 129
# VR0-[[0, 8), [8, 13), [13, 20), [20, 25), [25, 34), [34, 39), [39, 46), [46, 51), [51, 60), [60, 65), [65, 74), [74, 79), [79, 86), [86, 91), [91, 98), [98, 103), [103, 112), [112, 117), [117, 126), [126, 131), [131, 146), [146, 151), [151, 158), [158, 160), [160, 165), [165, 172), [172, 174), [174, 179), [179, 186), [186, 191), [191, 198), [198, 203), [203, 210), [210, 215), [215, 222), [222, 227), [227, 242), [242, 243)]-{0}-[84, 18, 96, 110, 144, 58, 72, 242, 44] --> $s0
# VR1-[[1, 8), [8, 13), [13, 20), [20, 25), [25, 34), [34, 39), [39, 46), [46, 51), [51, 60), [60, 65), [65, 74), [74, 79), [79, 86), [86, 91), [91, 98), [98, 103), [103, 112), [112, 117), [117, 125)]-{1}-[32, 124] --> $s1
# VR2-[[2, 4)]-{2}-[3] --> $s2
# VR2-[[5, 8), [8, 13), [13, 15)]-{3}-[7, 13, 14] --> $s2
# VR2-[[17, 20), [20, 25), [25, 34), [34, 39), [39, 46), [46, 51), [51, 60), [60, 65), [65, 74), [74, 79), [79, 86), [86, 91), [91, 98), [98, 103), [103, 112), [112, 117), [117, 126), [126, 131), [131, 146), [146, 151), [151, 158), [158, 160), [160, 165), [165, 172), [172, 174), [174, 179), [179, 186), [186, 191), [191, 198), [198, 203), [203, 210), [210, 215), [215, 222), [222, 227), [227, 242)]-{8}-[136, 184, 158, 172, 196, 229, 208] --> $s2
# VR2-[[256, 258)]-{128}-[257] --> $s0
# VR3-[[8, 10)]-{4}-[9] --> $s3
# VR3-[[10, 12)]-{5}-[11] --> $s3
# VR3-[[14, 16)]-{6}-[15] --> $s3
# VR3-[[15, 17)]-{7}-[16] --> $s2
# VR3-[[18, 20), [20, 25), [25, 29)]-{9}-[19, 26, 28] --> $s3
# VR3-[[31, 32)]-{15}-[] --> $s3
# VR3-[[32, 34), [34, 39), [39, 41)]-{16}-[33, 39, 40] --> $s3
# VR3-[[43, 44)]-{21}-[] --> $s3
# VR3-[[44, 46), [46, 51), [51, 55)]-{22}-[54, 52, 45] --> $s3
# VR3-[[57, 58)]-{28}-[] --> $s3
# VR3-[[58, 60), [60, 65), [65, 69)]-{29}-[68, 66, 59] --> $s3
# VR3-[[71, 72)]-{35}-[] --> $s3
# VR3-[[72, 74), [74, 79), [79, 81)]-{36}-[80, 79, 73] --> $s3
# VR3-[[83, 84)]-{41}-[] --> $s3
# VR3-[[84, 86), [86, 91), [91, 93)]-{42}-[85, 92, 91] --> $s3
# VR3-[[95, 96)]-{47}-[] --> $s3
# VR3-[[96, 98), [98, 103), [103, 107)]-{48}-[97, 106, 104] --> $s3
# VR3-[[109, 110)]-{54}-[] --> $s3
# VR3-[[110, 112), [112, 117), [117, 121)]-{55}-[118, 111, 120] --> $s3
# VR3-[[123, 124)]-{61}-[] --> $s3
# VR3-[[124, 126), [126, 131), [131, 141)]-{62}-[137, 140, 125] --> $s3
# VR3-[[143, 144)]-{70}-[] --> $s1
# VR3-[[144, 146), [146, 151), [151, 155)]-{71}-[152, 154, 145] --> $s1
# VR3-[[157, 158)]-{77}-[] --> $s1
# VR3-[[158, 160), [160, 165), [165, 167)]-{78}-[159, 166, 165] --> $s1
# VR3-[[169, 171)]-{83}-[170] --> $s1
# VR3-[[170, 172)]-{84}-[171] --> $s3
# VR3-[[172, 174), [174, 179), [179, 181)]-{85}-[173, 179, 180] --> $s1
# VR3-[[183, 186), [186, 191), [191, 198), [198, 203), [203, 210), [210, 215), [215, 222), [222, 227), [227, 229)]-{90}-[228] --> $s1
# VR3-[[240, 241)]-{120}-[] --> $s1
# VR3-[[242, 244), [244, 249), [249, 253)]-{121}-[252, 250, 243] --> $s1
# VR3-[[255, 257)]-{127}-[256] --> $s1
# VR4-[[20, 22)]-{10}-[21] --> $s4
# VR4-[[22, 24)]-{11}-[23] --> $s4
# VR4-[[25, 28)]-{12}-[27] --> $s4
# VR4-[[28, 30)]-{13}-[29] --> $s4
# VR4-[[29, 31)]-{14}-[30] --> $s3
# VR4-[[34, 36)]-{17}-[35] --> $s4
# VR4-[[36, 38)]-{18}-[37] --> $s4
# VR4-[[40, 42)]-{19}-[41] --> $s4
# VR4-[[41, 43)]-{20}-[42] --> $s3
# VR4-[[46, 48)]-{23}-[47] --> $s4
# VR4-[[48, 50)]-{24}-[49] --> $s4
# VR4-[[51, 54)]-{25}-[53] --> $s4
# VR4-[[54, 56)]-{26}-[55] --> $s4
# VR4-[[55, 57)]-{27}-[56] --> $s3
# VR4-[[60, 62)]-{30}-[61] --> $s4
# VR4-[[62, 64)]-{31}-[63] --> $s4
# VR4-[[65, 68)]-{32}-[67] --> $s4
# VR4-[[68, 70)]-{33}-[69] --> $s4
# VR4-[[69, 71)]-{34}-[70] --> $s3
# VR4-[[74, 76)]-{37}-[75] --> $s4
# VR4-[[76, 78)]-{38}-[77] --> $s4
# VR4-[[80, 82)]-{39}-[81] --> $s4
# VR4-[[81, 83)]-{40}-[82] --> $s3
# VR4-[[86, 88)]-{43}-[87] --> $s4
# VR4-[[88, 90)]-{44}-[89] --> $s4
# VR4-[[92, 94)]-{45}-[93] --> $s4
# VR4-[[93, 95)]-{46}-[94] --> $s3
# VR4-[[98, 100)]-{49}-[99] --> $s4
# VR4-[[100, 102)]-{50}-[101] --> $s4
# VR4-[[103, 106)]-{51}-[105] --> $s4
# VR4-[[106, 108)]-{52}-[107] --> $s4
# VR4-[[107, 109)]-{53}-[108] --> $s3
# VR4-[[112, 114)]-{56}-[113] --> $s4
# VR4-[[114, 116)]-{57}-[115] --> $s4
# VR4-[[117, 120)]-{58}-[119] --> $s4
# VR4-[[120, 122)]-{59}-[121] --> $s4
# VR4-[[121, 123)]-{60}-[122] --> $s3
# VR4-[[126, 128)]-{63}-[127] --> $s1
# VR4-[[128, 130)]-{64}-[129] --> $s1
# VR4-[[131, 133)]-{65}-[132] --> $s1
# VR4-[[134, 139)]-{66}-[138] --> $s1
# VR4-[[140, 142)]-{68}-[141] --> $s1
# VR4-[[141, 143)]-{69}-[142] --> $s3
# VR4-[[146, 148)]-{72}-[147] --> $s3
# VR4-[[148, 150)]-{73}-[149] --> $s3
# VR4-[[151, 154)]-{74}-[153] --> $s3
# VR4-[[154, 156)]-{75}-[155] --> $s3
# VR4-[[155, 157)]-{76}-[156] --> $s1
# VR4-[[160, 162)]-{79}-[161] --> $s3
# VR4-[[162, 164)]-{80}-[163] --> $s3
# VR4-[[166, 168)]-{81}-[167] --> $s3
# VR4-[[167, 169)]-{82}-[168] --> $s1
# VR4-[[174, 176)]-{86}-[175] --> $s3
# VR4-[[176, 178)]-{87}-[177] --> $s3
# VR4-[[180, 182)]-{88}-[181] --> $s3
# VR4-[[181, 183)]-{89}-[182] --> $s1
# VR4-[[184, 186), [186, 191), [191, 193)]-{91}-[185, 191, 192] --> $s3
# VR4-[[195, 198), [198, 203), [203, 210), [210, 215), [215, 221)]-{96}-[220] --> $s3
# VR4-[[239, 241)]-{119}-[240] --> $s3
# VR4-[[244, 246)]-{122}-[245] --> $s0
# VR4-[[246, 248)]-{123}-[247] --> $s0
# VR4-[[249, 252)]-{124}-[251] --> $s0
# VR4-[[252, 254)]-{125}-[253] --> $s0
# VR4-[[253, 255)]-{126}-[254] --> $s1
# VR5-[[136, 140)]-{67}-[139] --> $s4
# VR5-[[186, 188)]-{92}-[187] --> $s4
# VR5-[[188, 190)]-{93}-[189] --> $s4
# VR5-[[192, 194)]-{94}-[193] --> $s4
# VR5-[[193, 195)]-{95}-[194] --> $s3
# VR5-[[196, 198), [198, 203), [203, 205)]-{97}-[204, 203, 197] --> $s4
# VR5-[[207, 210), [210, 215), [215, 222), [222, 227), [227, 228)]-{102}-[227] --> $s4
# VR5-[[238, 240)]-{118}-[239] --> $s1
# VR6-[[198, 200)]-{98}-[199] --> $s5
# VR6-[[200, 202)]-{99}-[201] --> $s5
# VR6-[[204, 206)]-{100}-[205] --> $s5
# VR6-[[205, 207)]-{101}-[206] --> $s4
# VR6-[[208, 210), [210, 215), [215, 217)]-{103}-[216, 215, 209] --> $s5
# VR6-[[219, 220)]-{108}-[] --> $s5
# VR6-[[220, 222), [222, 227), [227, 235)]-{109}-[221, 234, 230] --> $s5
# VR6-[[237, 239)]-{117}-[238] --> $s3
# VR7-[[210, 212)]-{104}-[211] --> $s6
# VR7-[[212, 214)]-{105}-[213] --> $s6
# VR7-[[216, 218)]-{106}-[217] --> $s6
# VR7-[[217, 219)]-{107}-[218] --> $s5
# VR7-[[222, 224)]-{110}-[223] --> $s3
# VR7-[[224, 226)]-{111}-[225] --> $s3
# VR7-[[227, 232)]-{112}-[231] --> $s3
# VR7-[[234, 236)]-{115}-[235] --> $s1
# VR7-[[235, 237)]-{116}-[236] --> $s3
# VR8-[[228, 233)]-{113}-[232] --> $s4
# VR9-[[229, 234)]-{114}-[233] --> $s1
Main.gen_code:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s6, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 8 ($fp)
	la	$s2, LambdaListRef_protObj
	move	$a0, $s2
	jal	Object.copy
	move	$s2, $a0
	jal	LambdaListRef_init
	bnez	$s2, dispatch_notvoid58
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 434
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid58:
	move	$a0, $s2
	lw	$s3, 8 ($s2)
	lw	$s2, 28 ($s3)
	jalr	$s2
	move	$s2, $a0
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid59
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 436
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid59:
	la	$s4, str_const49
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 12 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s3, $s1
	bnez	$s3, dispatch_notvoid60
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 437
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid60:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 28 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid61
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 438
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid61:
	la	$s4, str_const50
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 12 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid62
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 439
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid62:
	la	$s4, str_const51
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 12 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid63
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 440
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid63:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 56 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid64
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 441
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid64:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 60 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid65
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 442
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid65:
	la	$s4, str_const52
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 12 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid66
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 443
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid66:
	la	$s4, str_const53
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 12 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s3, $s1
	bnez	$s3, dispatch_notvoid67
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 444
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid67:
	la	$s1, VarList_protObj
	move	$a0, $s1
	jal	Object.copy
	move	$s1, $a0
	jal	VarList_init
	move	$s4, $s2
	move	$a0, $s3
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s3)
	lw	$s3, 40 ($s1)
	jalr	$s3
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid68
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 445
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid68:
	la	$s3, str_const54
	move	$a0, $s1
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s3, 8 ($s1)
	lw	$s1, 12 ($s3)
	jalr	$s1
	move	$s1, $a0
loop_start1:
	move	$s1, $s2
	bnez	$s1, dispatch_notvoid69
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 446
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid69:
	move	$a0, $s1
	lw	$s3, 8 ($s1)
	lw	$s1, 12 ($s3)
	jalr	$s1
	move	$s1, $a0
	li	$t0, 1
	sub	$s3, $t0, $s1
	beqz	$s3, loop_end1
	move	$s1, $s2
	bnez	$s1, dispatch_notvoid70
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 447
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid70:
	move	$a0, $s1
	lw	$s3, 8 ($s1)
	lw	$s1, 16 ($s3)
	jalr	$s1
	move	$s1, $a0
	move	$s3, $s2
	bnez	$s3, dispatch_notvoid71
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 448
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid71:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 20 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s4, $s2
	bnez	$s4, dispatch_notvoid72
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 449
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid72:
	move	$a0, $s4
	lw	$s5, 8 ($s4)
	lw	$s4, 24 ($s5)
	jalr	$s4
	move	$s4, $a0
	move	$s5, $s2
	bnez	$s5, dispatch_notvoid73
	la	$s6, str_const0
	move	$a0, $s6
	li	$s6, 451
	sw	$s6, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid73:
	move	$a0, $s5
	lw	$s6, 8 ($s5)
	lw	$s5, 36 ($s6)
	jalr	$s5
	move	$s5, $a0
	move	$s5, $s3
	bnez	$s5, dispatch_notvoid74
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 452
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid74:
	move	$s3, $s4
	move	$s4, $s1
	move	$s1, $s2
	move	$a0, $s5
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s5)
	lw	$s3, 52 ($s1)
	jalr	$s3
	move	$s3, $a0
	move	$s1, $s3
	move	$s3, $s1
	move	$s1, $s3
	b	loop_start1
loop_end1:
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid75
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 455
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid75:
	la	$s0, str_const50
	move	$a0, $s1
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s1)
	lw	$s1, 12 ($s0)
	jalr	$s1
	move	$s1, $a0
	move	$s0, $s1
	move	$a0, $s0
	j	__Main.gen_code_epilogue
__Main.gen_code_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s6, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s5, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 12
	jr	$ra

# web count: 392
# VR0-[[0, 3), [3, 8), [8, 14), [14, 19), [19, 26), [26, 31), [31, 40), [40, 45), [45, 51), [51, 56), [56, 63), [63, 68), [68, 77), [77, 82), [82, 88), [88, 93), [93, 100), [100, 105), [105, 114), [114, 119), [119, 121), [121, 126), [126, 128), [128, 133), [133, 135), [135, 140), [140, 142), [142, 147), [147, 154), [154, 159), [159, 173), [173, 178), [178, 192), [192, 197), [197, 217), [217, 222), [222, 224), [224, 229), [229, 231), [231, 236), [236, 238), [238, 243), [243, 250), [250, 255), [255, 269), [269, 274), [274, 294), [294, 299), [299, 301), [301, 306), [306, 308), [308, 313), [313, 320), [320, 325), [325, 345), [345, 350), [350, 352), [352, 357), [357, 359), [359, 364), [364, 366), [366, 371), [371, 373), [373, 378), [378, 385), [385, 390), [390, 404), [404, 409), [409, 423), [423, 428), [428, 448), [448, 453), [453, 455), [455, 460), [460, 462), [462, 467), [467, 469), [469, 474), [474, 476), [476, 481), [481, 483), [483, 488), [488, 490), [490, 495), [495, 497), [497, 502), [502, 504), [504, 509), [509, 511), [511, 516), [516, 523), [523, 528), [528, 542), [542, 547), [547, 561), [561, 566), [566, 580), [580, 585), [585, 599), [599, 604), [604, 618), [618, 623), [623, 637), [637, 642), [642, 656), [656, 661), [661, 681), [681, 686), [686, 688), [688, 693), [693, 695), [695, 700), [700, 702), [702, 707), [707, 714), [714, 719), [719, 721), [721, 726), [726, 733), [733, 738), [738, 759), [759, 764), [764, 766), [766, 771), [771, 778), [778, 783), [783, 785), [785, 790), [790, 796)]-{0}-[686, 1, 140, 679, 402, 559, 133, 152, 700, 267, 24, 693, 171, 306, 654, 38, 446, 795, 521, 318, 190, 292, 540, 783, 299, 421, 776, 61, 343, 474, 350, 616, 467, 75, 222, 460, 764, 635, 453, 215, 757, 712, 509, 578, 236, 98, 719, 371, 502, 383, 229, 119, 357, 495, 731, 597, 488, 248, 112, 364, 126, 481] spilled
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s0
# VR1-[[12, 14), [14, 19), [19, 21)]-{6}-[19, 20, 13] --> $s0
# VR1-[[23, 24)]-{11}-[] --> $s0
# VR1-[[24, 26), [26, 31), [31, 35)]-{12}-[34, 32, 25] --> $s0
# VR1-[[37, 38)]-{18}-[] --> $s0
# VR1-[[38, 40), [40, 45), [45, 47)]-{19}-[39, 46, 45] --> $s0
# VR1-[[49, 51), [51, 56), [56, 58)]-{24}-[50, 57, 56] --> $s0
# VR1-[[60, 61)]-{29}-[] --> $s0
# VR1-[[61, 63), [63, 68), [68, 72)]-{30}-[69, 71, 62] --> $s0
# VR1-[[74, 75)]-{36}-[] --> $s0
# VR1-[[75, 77), [77, 82), [82, 84)]-{37}-[83, 82, 76] --> $s0
# VR1-[[86, 88), [88, 93), [93, 95)]-{42}-[87, 93, 94] --> $s0
# VR1-[[97, 98)]-{47}-[] --> $s0
# VR1-[[98, 100), [100, 105), [105, 109)]-{48}-[99, 108, 106] --> $s0
# VR1-[[111, 112)]-{54}-[] --> $s0
# VR1-[[112, 114), [114, 119), [119, 121), [121, 126), [126, 128), [128, 133), [133, 135), [135, 140), [140, 142), [142, 147), [147, 154), [154, 159), [159, 173), [173, 178), [178, 192), [192, 197), [197, 212)]-{55}-[113, 209, 211] --> $s0
# VR1-[[214, 215)]-{102}-[] --> $s0
# VR1-[[215, 217), [217, 222), [222, 224), [224, 229), [229, 231), [231, 236), [236, 238), [238, 243), [243, 250), [250, 255), [255, 269), [269, 274), [274, 289)]-{103}-[288, 216, 286] --> $s0
# VR1-[[291, 292)]-{138}-[] --> $s0
# VR1-[[292, 294), [294, 299), [299, 301), [301, 306), [306, 308), [308, 313), [313, 320), [320, 325), [325, 340)]-{139}-[339, 293, 337] --> $s0
# VR1-[[342, 343)]-{162}-[] --> $s0
# VR1-[[343, 345), [345, 350), [350, 352), [352, 357), [357, 359), [359, 364), [364, 366), [366, 371), [371, 373), [373, 378), [378, 385), [385, 390), [390, 404), [404, 409), [409, 423), [423, 428), [428, 443)]-{163}-[440, 442, 344] --> $s0
# VR1-[[445, 446)]-{210}-[] --> $s0
# VR1-[[446, 448), [448, 453), [453, 455), [455, 460), [460, 462), [462, 467), [467, 469), [469, 474), [474, 476), [476, 481), [481, 483), [483, 488), [488, 490), [490, 495), [495, 497), [497, 502), [502, 504), [504, 509), [509, 511), [511, 516), [516, 523), [523, 528), [528, 542), [542, 547), [547, 561), [561, 566), [566, 580), [580, 585), [585, 599), [599, 604), [604, 618), [618, 623), [623, 637), [637, 642), [642, 656), [656, 661), [661, 676)]-{211}-[447, 675, 673] spilled
# VR1-[[678, 679)]-{318}-[] --> $s0
# VR1-[[679, 681), [681, 686), [686, 688), [688, 693), [693, 695), [695, 700), [700, 702), [702, 707), [707, 714), [714, 719), [719, 721), [721, 726), [726, 733), [733, 738), [738, 759), [759, 764), [764, 766), [766, 771), [771, 778), [778, 783), [783, 785), [785, 790), [790, 797), [797, 802), [802, 831)]-{319}-[680, 828, 830] spilled
# VR1-[[833, 834)]-{390}-[] --> $s0
# VR1-[[834, 836)]-{391}-[835] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s1
# VR2-[[5, 7)]-{3}-[6] --> $s1
# VR2-[[9, 11)]-{4}-[10] --> $s1
# VR2-[[10, 12)]-{5}-[11] --> $s0
# VR2-[[14, 16)]-{7}-[15] --> $s1
# VR2-[[16, 18)]-{8}-[17] --> $s1
# VR2-[[20, 22)]-{9}-[21] --> $s1
# VR2-[[21, 23)]-{10}-[22] --> $s0
# VR2-[[26, 28)]-{13}-[27] --> $s1
# VR2-[[28, 30)]-{14}-[29] --> $s1
# VR2-[[31, 34)]-{15}-[33] --> $s1
# VR2-[[34, 36)]-{16}-[35] --> $s1
# VR2-[[35, 37)]-{17}-[36] --> $s0
# VR2-[[40, 42)]-{20}-[41] --> $s1
# VR2-[[42, 44)]-{21}-[43] --> $s1
# VR2-[[46, 48)]-{22}-[47] --> $s1
# VR2-[[47, 49)]-{23}-[48] --> $s0
# VR2-[[51, 53)]-{25}-[52] --> $s1
# VR2-[[53, 55)]-{26}-[54] --> $s1
# VR2-[[57, 59)]-{27}-[58] --> $s1
# VR2-[[58, 60)]-{28}-[59] --> $s0
# VR2-[[63, 65)]-{31}-[64] --> $s1
# VR2-[[65, 67)]-{32}-[66] --> $s1
# VR2-[[68, 71)]-{33}-[70] --> $s1
# VR2-[[71, 73)]-{34}-[72] --> $s1
# VR2-[[72, 74)]-{35}-[73] --> $s0
# VR2-[[77, 79)]-{38}-[78] --> $s1
# VR2-[[79, 81)]-{39}-[80] --> $s1
# VR2-[[83, 85)]-{40}-[84] --> $s1
# VR2-[[84, 86)]-{41}-[85] --> $s0
# VR2-[[88, 90)]-{43}-[89] --> $s1
# VR2-[[90, 92)]-{44}-[91] --> $s1
# VR2-[[94, 96)]-{45}-[95] --> $s1
# VR2-[[95, 97)]-{46}-[96] --> $s0
# VR2-[[100, 102)]-{49}-[101] --> $s1
# VR2-[[102, 104)]-{50}-[103] --> $s1
# VR2-[[105, 108)]-{51}-[107] --> $s1
# VR2-[[108, 110)]-{52}-[109] --> $s1
# VR2-[[109, 111)]-{53}-[110] --> $s0
# VR2-[[114, 116)]-{56}-[115] --> $s1
# VR2-[[116, 118)]-{57}-[117] --> $s1
# VR2-[[119, 121), [121, 126), [126, 128), [128, 133), [133, 135), [135, 140), [140, 142), [142, 147), [147, 154), [154, 159), [159, 173), [173, 178), [178, 192), [192, 197), [197, 206)]-{58}-[205, 202, 120] --> $s1
# VR2-[[208, 211)]-{99}-[210] --> $s1
# VR2-[[211, 213)]-{100}-[212] --> $s1
# VR2-[[212, 214)]-{101}-[213] --> $s0
# VR2-[[217, 219)]-{104}-[218] --> $s1
# VR2-[[219, 221)]-{105}-[220] --> $s1
# VR2-[[222, 224), [224, 229), [229, 231), [231, 236), [236, 238), [238, 243), [243, 250), [250, 255), [255, 269), [269, 274), [274, 283)]-{106}-[223, 279, 282] --> $s1
# VR2-[[285, 288)]-{135}-[287] --> $s1
# VR2-[[288, 290)]-{136}-[289] --> $s1
# VR2-[[289, 291)]-{137}-[290] --> $s0
# VR2-[[294, 296)]-{140}-[295] --> $s1
# VR2-[[296, 298)]-{141}-[297] --> $s1
# VR2-[[299, 301), [301, 306), [306, 308), [308, 313), [313, 320), [320, 325), [325, 334)]-{142}-[333, 300, 330] --> $s1
# VR2-[[336, 339)]-{159}-[338] --> $s1
# VR2-[[339, 341)]-{160}-[340] --> $s1
# VR2-[[340, 342)]-{161}-[341] --> $s0
# VR2-[[345, 347)]-{164}-[346] --> $s1
# VR2-[[347, 349)]-{165}-[348] --> $s1
# VR2-[[350, 352), [352, 357), [357, 359), [359, 364), [364, 366), [366, 371), [371, 373), [373, 378), [378, 385), [385, 390), [390, 404), [404, 409), [409, 423), [423, 428), [428, 437)]-{166}-[351, 433, 436] --> $s1
# VR2-[[439, 442)]-{207}-[441] --> $s1
# VR2-[[442, 444)]-{208}-[443] --> $s1
# VR2-[[443, 445)]-{209}-[444] --> $s0
# VR2-[[448, 450)]-{212}-[449] --> $s0
# VR2-[[450, 452)]-{213}-[451] --> $s0
# VR2-[[453, 455), [455, 460), [460, 462), [462, 467), [467, 469), [469, 474), [474, 476), [476, 481), [481, 483), [483, 488), [488, 490), [490, 495), [495, 497), [497, 502), [502, 504), [504, 509), [509, 511), [511, 516), [516, 523), [523, 528), [528, 542), [542, 547), [547, 561), [561, 566), [566, 580), [580, 585), [585, 599), [599, 604), [604, 618), [618, 623), [623, 637), [637, 642), [642, 656), [656, 661), [661, 670)]-{214}-[669, 666, 454] spilled
# VR2-[[672, 675)]-{315}-[674] --> $s0
# VR2-[[675, 677)]-{316}-[676] --> $s0
# VR2-[[676, 678)]-{317}-[677] --> $s1
# VR2-[[681, 683)]-{320}-[682] --> $s0
# VR2-[[683, 685)]-{321}-[684] --> $s0
# VR2-[[686, 688), [688, 693), [693, 695), [695, 700), [700, 702), [702, 707), [707, 714), [714, 719), [719, 721), [721, 726), [726, 733), [733, 738), [738, 759), [759, 764), [764, 766), [766, 771), [771, 778), [778, 783), [783, 785), [785, 790), [790, 797), [797, 802), [802, 825)]-{322}-[687, 821, 824] spilled
# VR2-[[827, 830)]-{387}-[829] --> $s0
# VR2-[[830, 832)]-{388}-[831] --> $s0
# VR2-[[831, 833)]-{389}-[832] --> $s1
# VR3-[[121, 123)]-{59}-[122] --> $s2
# VR3-[[123, 125)]-{60}-[124] --> $s2
# VR3-[[126, 128), [128, 133), [133, 135), [135, 140), [140, 142), [142, 147), [147, 154), [154, 159), [159, 173), [173, 178), [178, 187)]-{61}-[186, 127, 183] --> $s2
# VR3-[[189, 192), [192, 197), [197, 204)]-{90}-[203] --> $s2
# VR3-[[205, 207)]-{97}-[206] --> $s2
# VR3-[[206, 208)]-{98}-[207] --> $s1
# VR3-[[224, 226)]-{107}-[225] --> $s2
# VR3-[[226, 228)]-{108}-[227] --> $s2
# VR3-[[229, 231), [231, 236), [236, 238), [238, 243), [243, 250), [250, 255), [255, 264)]-{109}-[263, 260, 230] --> $s2
# VR3-[[266, 269), [269, 274), [274, 281)]-{126}-[280] --> $s2
# VR3-[[282, 284)]-{133}-[283] --> $s2
# VR3-[[283, 285)]-{134}-[284] --> $s1
# VR3-[[301, 303)]-{143}-[302] --> $s2
# VR3-[[303, 305)]-{144}-[304] --> $s2
# VR3-[[306, 308), [308, 313), [313, 315)]-{145}-[307, 313, 314] --> $s2
# VR3-[[317, 320), [320, 325), [325, 332)]-{150}-[331] --> $s2
# VR3-[[333, 335)]-{157}-[334] --> $s2
# VR3-[[334, 336)]-{158}-[335] --> $s1
# VR3-[[352, 354)]-{167}-[353] --> $s2
# VR3-[[354, 356)]-{168}-[355] --> $s2
# VR3-[[357, 359), [359, 364), [364, 366), [366, 371), [371, 373), [373, 378), [378, 385), [385, 390), [390, 404), [404, 409), [409, 418)]-{169}-[358, 414, 417] --> $s2
# VR3-[[420, 423), [423, 428), [428, 435)]-{198}-[434] --> $s2
# VR3-[[436, 438)]-{205}-[437] --> $s2
# VR3-[[437, 439)]-{206}-[438] --> $s1
# VR3-[[455, 457)]-{215}-[456] --> $s0
# VR3-[[457, 459)]-{216}-[458] --> $s0
# VR3-[[460, 462), [462, 467), [467, 469), [469, 474), [474, 476), [476, 481), [481, 483), [483, 488), [488, 490), [490, 495), [495, 497), [497, 502), [502, 504), [504, 509), [509, 511), [511, 516), [516, 523), [523, 528), [528, 542), [542, 547), [547, 561), [561, 566), [566, 580), [580, 585), [585, 599), [599, 604), [604, 618), [618, 623), [623, 637), [637, 642), [642, 651)]-{217}-[461, 650, 647] spilled
# VR3-[[653, 656), [656, 661), [661, 668)]-{306}-[667] --> $s0
# VR3-[[669, 671)]-{313}-[670] --> $s0
# VR3-[[670, 672)]-{314}-[671] --> $s1
# VR3-[[688, 690)]-{323}-[689] --> $s0
# VR3-[[690, 692)]-{324}-[691] --> $s0
# VR3-[[693, 695), [695, 700), [700, 702), [702, 707), [707, 714), [714, 719), [719, 721), [721, 726), [726, 733), [733, 738), [738, 754)]-{325}-[750, 694, 753] --> $s0
# VR3-[[756, 759), [759, 764), [764, 766), [766, 771), [771, 778), [778, 783), [783, 785), [785, 790), [790, 797), [797, 802), [802, 823)]-{354}-[822] --> $s0
# VR3-[[824, 826)]-{385}-[825] --> $s0
# VR3-[[825, 827)]-{386}-[826] --> $s1
# VR4-[[128, 130)]-{62}-[129] --> $s3
# VR4-[[130, 132)]-{63}-[131] --> $s3
# VR4-[[133, 135), [135, 140), [140, 142), [142, 147), [147, 154), [154, 159), [159, 168)]-{64}-[167, 134, 164] --> $s3
# VR4-[[170, 173), [173, 178), [178, 185)]-{81}-[184] --> $s3
# VR4-[[186, 188)]-{88}-[187] --> $s3
# VR4-[[187, 189)]-{89}-[188] --> $s2
# VR4-[[190, 192), [192, 197), [197, 199)]-{91}-[191, 197, 198] --> $s3
# VR4-[[201, 205)]-{96}-[204] --> $s3
# VR4-[[231, 233)]-{110}-[232] --> $s3
# VR4-[[233, 235)]-{111}-[234] --> $s3
# VR4-[[236, 238), [238, 243), [243, 245)]-{112}-[237, 244, 243] --> $s3
# VR4-[[247, 250), [250, 255), [255, 262)]-{117}-[261] --> $s3
# VR4-[[263, 265)]-{124}-[264] --> $s3
# VR4-[[264, 266)]-{125}-[265] --> $s2
# VR4-[[267, 269), [269, 274), [274, 276)]-{127}-[275, 274, 268] --> $s3
# VR4-[[278, 282)]-{132}-[281] --> $s3
# VR4-[[308, 310)]-{146}-[309] --> $s3
# VR4-[[310, 312)]-{147}-[311] --> $s3
# VR4-[[314, 316)]-{148}-[315] --> $s3
# VR4-[[315, 317)]-{149}-[316] --> $s2
# VR4-[[318, 320), [320, 325), [325, 327)]-{151}-[326, 325, 319] --> $s3
# VR4-[[329, 333)]-{156}-[332] --> $s3
# VR4-[[359, 361)]-{170}-[360] --> $s3
# VR4-[[361, 363)]-{171}-[362] --> $s3
# VR4-[[364, 366), [366, 371), [371, 373), [373, 378), [378, 385), [385, 390), [390, 399)]-{172}-[395, 398, 365] --> $s3
# VR4-[[401, 404), [404, 409), [409, 416)]-{189}-[415] --> $s3
# VR4-[[417, 419)]-{196}-[418] --> $s3
# VR4-[[418, 420)]-{197}-[419] --> $s2
# VR4-[[421, 423), [423, 428), [428, 430)]-{199}-[429, 428, 422] --> $s3
# VR4-[[432, 436)]-{204}-[435] --> $s3
# VR4-[[462, 464)]-{218}-[463] --> $s0
# VR4-[[464, 466)]-{219}-[465] --> $s0
# VR4-[[467, 469), [469, 474), [474, 476), [476, 481), [481, 483), [483, 488), [488, 490), [490, 495), [495, 497), [497, 502), [502, 504), [504, 509), [509, 511), [511, 516), [516, 523), [523, 528), [528, 542), [542, 547), [547, 561), [561, 566), [566, 580), [580, 585), [585, 599), [599, 604), [604, 618), [618, 623), [623, 632)]-{220}-[631, 628, 468] spilled
# VR4-[[634, 637), [637, 642), [642, 649)]-{297}-[648] --> $s0
# VR4-[[650, 652)]-{304}-[651] --> $s0
# VR4-[[651, 653)]-{305}-[652] --> $s1
# VR4-[[654, 656), [656, 661), [661, 663)]-{307}-[655, 661, 662] --> $s1
# VR4-[[665, 669)]-{312}-[668] --> $s1
# VR4-[[695, 697)]-{326}-[696] --> $s1
# VR4-[[697, 699)]-{327}-[698] --> $s1
# VR4-[[700, 702), [702, 707), [707, 709)]-{328}-[701, 707, 708] --> $s1
# VR4-[[711, 714), [714, 719), [719, 721), [721, 726), [726, 733), [733, 738), [738, 752)]-{333}-[751] --> $s1
# VR4-[[753, 755)]-{352}-[754] --> $s1
# VR4-[[754, 756)]-{353}-[755] --> $s0
# VR4-[[757, 759), [759, 764), [764, 766), [766, 771), [771, 778), [778, 783), [783, 785), [785, 790), [790, 797), [797, 802), [802, 818)]-{355}-[817, 814, 758] --> $s1
# VR4-[[820, 824)]-{384}-[823] --> $s1
# VR5-[[135, 137)]-{65}-[136] --> $s4
# VR5-[[137, 139)]-{66}-[138] --> $s4
# VR5-[[140, 142), [142, 147), [147, 149)]-{67}-[141, 147, 148] --> $s4
# VR5-[[151, 154), [154, 159), [159, 166)]-{72}-[165] --> $s4
# VR5-[[167, 169)]-{79}-[168] --> $s4
# VR5-[[168, 170)]-{80}-[169] --> $s3
# VR5-[[171, 173), [173, 178), [178, 180)]-{82}-[172, 178, 179] --> $s4
# VR5-[[182, 186)]-{87}-[185] --> $s4
# VR5-[[192, 194)]-{92}-[193] --> $s4
# VR5-[[194, 196)]-{93}-[195] --> $s4
# VR5-[[198, 200)]-{94}-[199] --> $s4
# VR5-[[199, 201)]-{95}-[200] --> $s3
# VR5-[[238, 240)]-{113}-[239] --> $s4
# VR5-[[240, 242)]-{114}-[241] --> $s4
# VR5-[[244, 246)]-{115}-[245] --> $s4
# VR5-[[245, 247)]-{116}-[246] --> $s3
# VR5-[[248, 250), [250, 255), [255, 257)]-{118}-[255, 256, 249] --> $s4
# VR5-[[259, 263)]-{123}-[262] --> $s4
# VR5-[[269, 271)]-{128}-[270] --> $s4
# VR5-[[271, 273)]-{129}-[272] --> $s4
# VR5-[[275, 277)]-{130}-[276] --> $s4
# VR5-[[276, 278)]-{131}-[277] --> $s3
# VR5-[[320, 322)]-{152}-[321] --> $s4
# VR5-[[322, 324)]-{153}-[323] --> $s4
# VR5-[[326, 328)]-{154}-[327] --> $s4
# VR5-[[327, 329)]-{155}-[328] --> $s3
# VR5-[[366, 368)]-{173}-[367] --> $s4
# VR5-[[368, 370)]-{174}-[369] --> $s4
# VR5-[[371, 373), [373, 378), [378, 380)]-{175}-[372, 379, 378] --> $s4
# VR5-[[382, 385), [385, 390), [390, 397)]-{180}-[396] --> $s4
# VR5-[[398, 400)]-{187}-[399] --> $s4
# VR5-[[399, 401)]-{188}-[400] --> $s3
# VR5-[[402, 404), [404, 409), [409, 411)]-{190}-[410, 409, 403] --> $s4
# VR5-[[413, 417)]-{195}-[416] --> $s4
# VR5-[[423, 425)]-{200}-[424] --> $s4
# VR5-[[425, 427)]-{201}-[426] --> $s4
# VR5-[[429, 431)]-{202}-[430] --> $s4
# VR5-[[430, 432)]-{203}-[431] --> $s3
# VR5-[[469, 471)]-{221}-[470] --> $s0
# VR5-[[471, 473)]-{222}-[472] --> $s0
# VR5-[[474, 476), [476, 481), [481, 483), [483, 488), [488, 490), [490, 495), [495, 497), [497, 502), [502, 504), [504, 509), [509, 511), [511, 516), [516, 523), [523, 528), [528, 542), [542, 547), [547, 561), [561, 566), [566, 580), [580, 585), [585, 599), [599, 604), [604, 613)]-{223}-[609, 475, 612] spilled
# VR5-[[615, 618), [618, 623), [623, 630)]-{288}-[629] --> $s0
# VR5-[[631, 633)]-{295}-[632] --> $s0
# VR5-[[632, 634)]-{296}-[633] --> $s1
# VR5-[[635, 637), [637, 642), [642, 644)]-{298}-[643, 636, 642] --> $s1
# VR5-[[646, 650)]-{303}-[649] --> $s1
# VR5-[[656, 658)]-{308}-[657] --> $s2
# VR5-[[658, 660)]-{309}-[659] --> $s2
# VR5-[[662, 664)]-{310}-[663] --> $s2
# VR5-[[663, 665)]-{311}-[664] --> $s1
# VR5-[[702, 704)]-{329}-[703] --> $s2
# VR5-[[704, 706)]-{330}-[705] --> $s2
# VR5-[[708, 710)]-{331}-[709] --> $s2
# VR5-[[709, 711)]-{332}-[710] --> $s1
# VR5-[[712, 714), [714, 719), [719, 721), [721, 726), [726, 733), [733, 738), [738, 747)]-{334}-[713, 746, 743] --> $s2
# VR5-[[749, 753)]-{351}-[752] --> $s2
# VR5-[[759, 761)]-{356}-[760] --> $s2
# VR5-[[761, 763)]-{357}-[762] --> $s2
# VR5-[[764, 766), [766, 771), [771, 773)]-{358}-[772, 771, 765] --> $s2
# VR5-[[775, 778), [778, 783), [783, 785), [785, 790), [790, 797), [797, 802), [802, 816)]-{363}-[815] --> $s2
# VR5-[[817, 819)]-{382}-[818] --> $s2
# VR5-[[818, 820)]-{383}-[819] --> $s1
# VR6-[[142, 144)]-{68}-[143] --> $s5
# VR6-[[144, 146)]-{69}-[145] --> $s5
# VR6-[[148, 150)]-{70}-[149] --> $s5
# VR6-[[149, 151)]-{71}-[150] --> $s4
# VR6-[[152, 154), [154, 159), [159, 161)]-{73}-[153, 159, 160] --> $s5
# VR6-[[163, 167)]-{78}-[166] --> $s5
# VR6-[[173, 175)]-{83}-[174] --> $s5
# VR6-[[175, 177)]-{84}-[176] --> $s5
# VR6-[[179, 181)]-{85}-[180] --> $s5
# VR6-[[180, 182)]-{86}-[181] --> $s4
# VR6-[[250, 252)]-{119}-[251] --> $s5
# VR6-[[252, 254)]-{120}-[253] --> $s5
# VR6-[[256, 258)]-{121}-[257] --> $s5
# VR6-[[257, 259)]-{122}-[258] --> $s4
# VR6-[[373, 375)]-{176}-[374] --> $s5
# VR6-[[375, 377)]-{177}-[376] --> $s5
# VR6-[[379, 381)]-{178}-[380] --> $s5
# VR6-[[380, 382)]-{179}-[381] --> $s4
# VR6-[[383, 385), [385, 390), [390, 392)]-{181}-[384, 391, 390] --> $s5
# VR6-[[394, 398)]-{186}-[397] --> $s5
# VR6-[[404, 406)]-{191}-[405] --> $s5
# VR6-[[406, 408)]-{192}-[407] --> $s5
# VR6-[[410, 412)]-{193}-[411] --> $s5
# VR6-[[411, 413)]-{194}-[412] --> $s4
# VR6-[[476, 478)]-{224}-[477] --> $s0
# VR6-[[478, 480)]-{225}-[479] --> $s0
# VR6-[[481, 483), [483, 488), [488, 490), [490, 495), [495, 497), [497, 502), [502, 504), [504, 509), [509, 511), [511, 516), [516, 523), [523, 528), [528, 542), [542, 547), [547, 561), [561, 566), [566, 580), [580, 585), [585, 594)]-{226}-[593, 590, 482] --> $s0
# VR6-[[596, 599), [599, 604), [604, 611)]-{279}-[610] --> $s0
# VR6-[[612, 614)]-{286}-[613] --> $s0
# VR6-[[613, 615)]-{287}-[614] --> $s1
# VR6-[[616, 618), [618, 623), [623, 625)]-{289}-[624, 617, 623] --> $s1
# VR6-[[627, 631)]-{294}-[630] --> $s1
# VR6-[[637, 639)]-{299}-[638] --> $s2
# VR6-[[639, 641)]-{300}-[640] --> $s2
# VR6-[[643, 645)]-{301}-[644] --> $s2
# VR6-[[644, 646)]-{302}-[645] --> $s1
# VR6-[[714, 716)]-{335}-[715] --> $s3
# VR6-[[716, 718)]-{336}-[717] --> $s3
# VR6-[[719, 721), [721, 726), [726, 728)]-{337}-[720, 726, 727] --> $s3
# VR6-[[730, 733), [733, 738), [738, 745)]-{342}-[744] --> $s3
# VR6-[[746, 748)]-{349}-[747] --> $s3
# VR6-[[747, 749)]-{350}-[748] --> $s2
# VR6-[[766, 768)]-{359}-[767] --> $s3
# VR6-[[768, 770)]-{360}-[769] --> $s3
# VR6-[[772, 774)]-{361}-[773] --> $s3
# VR6-[[773, 775)]-{362}-[774] --> $s2
# VR6-[[776, 778), [778, 783), [783, 785), [785, 790), [790, 797), [797, 802), [802, 811)]-{364}-[807, 810, 777] --> $s3
# VR6-[[813, 817)]-{381}-[816] --> $s3
# VR7-[[154, 156)]-{74}-[155] --> $s6
# VR7-[[156, 158)]-{75}-[157] --> $s6
# VR7-[[160, 162)]-{76}-[161] --> $s6
# VR7-[[161, 163)]-{77}-[162] --> $s5
# VR7-[[385, 387)]-{182}-[386] --> $s6
# VR7-[[387, 389)]-{183}-[388] --> $s6
# VR7-[[391, 393)]-{184}-[392] --> $s6
# VR7-[[392, 394)]-{185}-[393] --> $s5
# VR7-[[483, 485)]-{227}-[484] --> $s1
# VR7-[[485, 487)]-{228}-[486] --> $s1
# VR7-[[488, 490), [490, 495), [495, 497), [497, 502), [502, 504), [504, 509), [509, 511), [511, 516), [516, 523), [523, 528), [528, 542), [542, 547), [547, 561), [561, 566), [566, 575)]-{229}-[489, 574, 571] --> $s1
# VR7-[[577, 580), [580, 585), [585, 592)]-{270}-[591] --> $s1
# VR7-[[593, 595)]-{277}-[594] --> $s1
# VR7-[[594, 596)]-{278}-[595] --> $s0
# VR7-[[597, 599), [599, 604), [604, 606)]-{280}-[598, 605, 604] --> $s1
# VR7-[[608, 612)]-{285}-[611] --> $s1
# VR7-[[618, 620)]-{290}-[619] --> $s2
# VR7-[[620, 622)]-{291}-[621] --> $s2
# VR7-[[624, 626)]-{292}-[625] --> $s2
# VR7-[[625, 627)]-{293}-[626] --> $s1
# VR7-[[721, 723)]-{338}-[722] --> $s4
# VR7-[[723, 725)]-{339}-[724] --> $s4
# VR7-[[727, 729)]-{340}-[728] --> $s4
# VR7-[[728, 730)]-{341}-[729] --> $s3
# VR7-[[731, 733), [733, 738), [738, 740)]-{343}-[732, 739, 738] --> $s4
# VR7-[[742, 746)]-{348}-[745] --> $s4
# VR7-[[778, 780)]-{365}-[779] --> $s4
# VR7-[[780, 782)]-{366}-[781] --> $s4
# VR7-[[783, 785), [785, 790), [790, 792)]-{367}-[791, 790, 784] --> $s4
# VR7-[[794, 797), [797, 802), [802, 809)]-{372}-[808] --> $s4
# VR7-[[810, 812)]-{379}-[811] --> $s4
# VR7-[[811, 813)]-{380}-[812] --> $s3
# VR8-[[490, 492)]-{230}-[491] --> $s2
# VR8-[[492, 494)]-{231}-[493] --> $s2
# VR8-[[495, 497), [497, 502), [502, 504), [504, 509), [509, 511), [511, 516), [516, 523), [523, 528), [528, 542), [542, 547), [547, 556)]-{232}-[496, 555, 552] --> $s2
# VR8-[[558, 561), [561, 566), [566, 573)]-{261}-[572] --> $s2
# VR8-[[574, 576)]-{268}-[575] --> $s2
# VR8-[[575, 577)]-{269}-[576] --> $s1
# VR8-[[578, 580), [580, 585), [585, 587)]-{271}-[579, 585, 586] --> $s2
# VR8-[[589, 593)]-{276}-[592] --> $s2
# VR8-[[599, 601)]-{281}-[600] --> $s2
# VR8-[[601, 603)]-{282}-[602] --> $s2
# VR8-[[605, 607)]-{283}-[606] --> $s2
# VR8-[[606, 608)]-{284}-[607] --> $s1
# VR8-[[733, 735)]-{344}-[734] --> $s5
# VR8-[[735, 737)]-{345}-[736] --> $s5
# VR8-[[739, 741)]-{346}-[740] --> $s5
# VR8-[[740, 742)]-{347}-[741] --> $s4
# VR8-[[785, 787)]-{368}-[786] --> $s5
# VR8-[[787, 789)]-{369}-[788] --> $s5
# VR8-[[791, 793)]-{370}-[792] --> $s5
# VR8-[[792, 794)]-{371}-[793] --> $s4
# VR8-[[795, 797), [797, 802), [802, 804)]-{373}-[802, 803, 796] --> $s5
# VR8-[[806, 810)]-{378}-[809] --> $s5
# VR9-[[497, 499)]-{233}-[498] --> $s3
# VR9-[[499, 501)]-{234}-[500] --> $s3
# VR9-[[502, 504), [504, 509), [509, 511), [511, 516), [516, 523), [523, 528), [528, 537)]-{235}-[533, 503, 536] --> $s3
# VR9-[[539, 542), [542, 547), [547, 554)]-{252}-[553] --> $s3
# VR9-[[555, 557)]-{259}-[556] --> $s3
# VR9-[[556, 558)]-{260}-[557] --> $s2
# VR9-[[559, 561), [561, 566), [566, 568)]-{262}-[567, 566, 560] --> $s3
# VR9-[[570, 574)]-{267}-[573] --> $s3
# VR9-[[580, 582)]-{272}-[581] --> $s3
# VR9-[[582, 584)]-{273}-[583] --> $s3
# VR9-[[586, 588)]-{274}-[587] --> $s3
# VR9-[[587, 589)]-{275}-[588] --> $s2
# VR9-[[797, 799)]-{374}-[798] --> $s6
# VR9-[[799, 801)]-{375}-[800] --> $s6
# VR9-[[803, 805)]-{376}-[804] --> $s6
# VR9-[[804, 806)]-{377}-[805] --> $s5
# VR10-[[504, 506)]-{236}-[505] --> $s4
# VR10-[[506, 508)]-{237}-[507] --> $s4
# VR10-[[509, 511), [511, 516), [516, 518)]-{238}-[516, 517, 510] --> $s4
# VR10-[[520, 523), [523, 528), [528, 535)]-{243}-[534] --> $s4
# VR10-[[536, 538)]-{250}-[537] --> $s4
# VR10-[[537, 539)]-{251}-[538] --> $s3
# VR10-[[540, 542), [542, 547), [547, 549)]-{253}-[548, 547, 541] --> $s4
# VR10-[[551, 555)]-{258}-[554] --> $s4
# VR10-[[561, 563)]-{263}-[562] --> $s4
# VR10-[[563, 565)]-{264}-[564] --> $s4
# VR10-[[567, 569)]-{265}-[568] --> $s4
# VR10-[[568, 570)]-{266}-[569] --> $s3
# VR11-[[511, 513)]-{239}-[512] --> $s5
# VR11-[[513, 515)]-{240}-[514] --> $s5
# VR11-[[517, 519)]-{241}-[518] --> $s5
# VR11-[[518, 520)]-{242}-[519] --> $s4
# VR11-[[521, 523), [523, 528), [528, 530)]-{244}-[529, 528, 522] --> $s5
# VR11-[[532, 536)]-{249}-[535] --> $s5
# VR11-[[542, 544)]-{254}-[543] --> $s5
# VR11-[[544, 546)]-{255}-[545] --> $s5
# VR11-[[548, 550)]-{256}-[549] --> $s5
# VR11-[[549, 551)]-{257}-[550] --> $s4
# VR12-[[523, 525)]-{245}-[524] --> $s6
# VR12-[[525, 527)]-{246}-[526] --> $s6
# VR12-[[529, 531)]-{247}-[530] --> $s6
# VR12-[[530, 532)]-{248}-[531] --> $s5
Main.main:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	addi	 $sp, $sp, -32
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s6, 0 ($sp)
	addi $sp, $sp, -4
	move	$t0, $a0
	sw	$t0, -4 ($fp)
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid76
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 461
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid76:
	move	$a0, $s0
	lw	$s1, 8 ($s0)
	lw	$s0, 40 ($s1)
	jalr	$s0
	move	$s0, $a0
	bnez	$s0, dispatch_notvoid77
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 461
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid77:
	move	$a0, $s0
	lw	$s1, 8 ($s0)
	lw	$s0, 28 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid78
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 462
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid78:
	la	$s1, str_const1
	move	$a0, $s0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s0)
	lw	$s0, 12 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid79
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 463
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid79:
	move	$a0, $s0
	lw	$s1, 8 ($s0)
	lw	$s0, 44 ($s1)
	jalr	$s0
	move	$s0, $a0
	bnez	$s0, dispatch_notvoid80
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 463
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid80:
	move	$a0, $s0
	lw	$s1, 8 ($s0)
	lw	$s0, 28 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid81
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 464
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid81:
	la	$s1, str_const1
	move	$a0, $s0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s0)
	lw	$s0, 12 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid82
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 465
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid82:
	move	$a0, $s0
	lw	$s1, 8 ($s0)
	lw	$s0, 48 ($s1)
	jalr	$s0
	move	$s0, $a0
	bnez	$s0, dispatch_notvoid83
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 465
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid83:
	move	$a0, $s0
	lw	$s1, 8 ($s0)
	lw	$s0, 28 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid84
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 466
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid84:
	la	$s1, str_const1
	move	$a0, $s0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s0)
	lw	$s0, 12 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid85
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 467
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid85:
	lw	$t1, -4 ($fp)
	move	$s1, $t1
	bnez	$s1, dispatch_notvoid86
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 467
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid86:
	lw	$t1, -4 ($fp)
	move	$s2, $t1
	bnez	$s2, dispatch_notvoid87
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 467
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid87:
	lw	$t1, -4 ($fp)
	move	$s3, $t1
	bnez	$s3, dispatch_notvoid88
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 467
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid88:
	lw	$t1, -4 ($fp)
	move	$s4, $t1
	bnez	$s4, dispatch_notvoid89
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 467
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid89:
	move	$a0, $s4
	lw	$s5, 8 ($s4)
	lw	$s4, 48 ($s5)
	jalr	$s4
	move	$s4, $a0
	lw	$t1, -4 ($fp)
	move	$s5, $t1
	bnez	$s5, dispatch_notvoid90
	la	$s6, str_const0
	move	$a0, $s6
	li	$s6, 467
	sw	$s6, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid90:
	move	$a0, $s5
	lw	$s6, 8 ($s5)
	lw	$s5, 44 ($s6)
	jalr	$s5
	move	$s5, $a0
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 36 ($s4)
	jalr	$s3
	move	$s3, $a0
	lw	$t1, -4 ($fp)
	move	$s4, $t1
	bnez	$s4, dispatch_notvoid91
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 467
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid91:
	move	$a0, $s4
	lw	$s5, 8 ($s4)
	lw	$s4, 40 ($s5)
	jalr	$s4
	move	$s4, $a0
	move	$a0, $s2
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s3, 8 ($s2)
	lw	$s2, 36 ($s3)
	jalr	$s2
	move	$s2, $a0
	lw	$t1, -4 ($fp)
	move	$s3, $t1
	bnez	$s3, dispatch_notvoid92
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 467
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid92:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 40 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 36 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$a0, $s0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s0)
	lw	$s0, 52 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid93
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 468
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid93:
	lw	$t1, -4 ($fp)
	move	$s1, $t1
	bnez	$s1, dispatch_notvoid94
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 468
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid94:
	lw	$t1, -4 ($fp)
	move	$s2, $t1
	bnez	$s2, dispatch_notvoid95
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 468
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid95:
	lw	$t1, -4 ($fp)
	move	$s3, $t1
	bnez	$s3, dispatch_notvoid96
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 468
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid96:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 44 ($s4)
	jalr	$s3
	move	$s3, $a0
	lw	$t1, -4 ($fp)
	move	$s4, $t1
	bnez	$s4, dispatch_notvoid97
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 468
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid97:
	move	$a0, $s4
	lw	$s5, 8 ($s4)
	lw	$s4, 40 ($s5)
	jalr	$s4
	move	$s4, $a0
	move	$a0, $s2
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s3, 8 ($s2)
	lw	$s2, 36 ($s3)
	jalr	$s2
	move	$s2, $a0
	lw	$t1, -4 ($fp)
	move	$s3, $t1
	bnez	$s3, dispatch_notvoid98
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 468
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid98:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 40 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 36 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$a0, $s0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s0)
	lw	$s0, 52 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid99
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 469
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid99:
	lw	$t1, -4 ($fp)
	move	$s1, $t1
	bnez	$s1, dispatch_notvoid100
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 469
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid100:
	lw	$t1, -4 ($fp)
	move	$s2, $t1
	bnez	$s2, dispatch_notvoid101
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 469
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid101:
	move	$a0, $s2
	lw	$s3, 8 ($s2)
	lw	$s2, 40 ($s3)
	jalr	$s2
	move	$s2, $a0
	lw	$t1, -4 ($fp)
	move	$s3, $t1
	bnez	$s3, dispatch_notvoid102
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 469
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid102:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 40 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 36 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$a0, $s0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s0)
	lw	$s0, 64 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid103
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 470
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid103:
	lw	$t1, -4 ($fp)
	move	$s1, $t1
	bnez	$s1, dispatch_notvoid104
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 470
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid104:
	lw	$t1, -4 ($fp)
	move	$s2, $t1
	bnez	$s2, dispatch_notvoid105
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 470
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid105:
	lw	$t1, -4 ($fp)
	move	$s3, $t1
	bnez	$s3, dispatch_notvoid106
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 470
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid106:
	lw	$t1, -4 ($fp)
	move	$s4, $t1
	bnez	$s4, dispatch_notvoid107
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 470
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid107:
	move	$a0, $s4
	lw	$s5, 8 ($s4)
	lw	$s4, 48 ($s5)
	jalr	$s4
	move	$s4, $a0
	lw	$t1, -4 ($fp)
	move	$s5, $t1
	bnez	$s5, dispatch_notvoid108
	la	$s6, str_const0
	move	$a0, $s6
	li	$s6, 470
	sw	$s6, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid108:
	move	$a0, $s5
	lw	$s6, 8 ($s5)
	lw	$s5, 44 ($s6)
	jalr	$s5
	move	$s5, $a0
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 36 ($s4)
	jalr	$s3
	move	$s3, $a0
	lw	$t1, -4 ($fp)
	move	$s4, $t1
	bnez	$s4, dispatch_notvoid109
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 470
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid109:
	move	$a0, $s4
	lw	$s5, 8 ($s4)
	lw	$s4, 40 ($s5)
	jalr	$s4
	move	$s4, $a0
	move	$a0, $s2
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s3, 8 ($s2)
	lw	$s2, 36 ($s3)
	jalr	$s2
	move	$s2, $a0
	lw	$t1, -4 ($fp)
	move	$s3, $t1
	bnez	$s3, dispatch_notvoid110
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 470
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid110:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 40 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 36 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$a0, $s0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s0)
	lw	$s0, 64 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$t0, $t1
	sw	$t0, -8 ($fp)
	lw	$t0, -8 ($fp)
	bnez	$t0, dispatch_notvoid111
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 471
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid111:
	lw	$t1, -4 ($fp)
	move	$t0, $t1
	sw	$t0, -16 ($fp)
	lw	$t0, -16 ($fp)
	bnez	$t0, dispatch_notvoid112
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 471
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid112:
	lw	$t1, -4 ($fp)
	move	$t0, $t1
	sw	$t0, -24 ($fp)
	lw	$t0, -24 ($fp)
	bnez	$t0, dispatch_notvoid113
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 471
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid113:
	lw	$t1, -4 ($fp)
	move	$t0, $t1
	sw	$t0, -28 ($fp)
	lw	$t0, -28 ($fp)
	bnez	$t0, dispatch_notvoid114
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 471
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid114:
	lw	$t1, -4 ($fp)
	move	$t0, $t1
	sw	$t0, -32 ($fp)
	lw	$t0, -32 ($fp)
	bnez	$t0, dispatch_notvoid115
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 471
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid115:
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid116
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 471
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid116:
	lw	$t1, -4 ($fp)
	move	$s1, $t1
	bnez	$s1, dispatch_notvoid117
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 471
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid117:
	lw	$t1, -4 ($fp)
	move	$s2, $t1
	bnez	$s2, dispatch_notvoid118
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 471
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid118:
	lw	$t1, -4 ($fp)
	move	$s3, $t1
	bnez	$s3, dispatch_notvoid119
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 471
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid119:
	lw	$t1, -4 ($fp)
	move	$s4, $t1
	bnez	$s4, dispatch_notvoid120
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 471
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid120:
	move	$a0, $s4
	lw	$s5, 8 ($s4)
	lw	$s4, 40 ($s5)
	jalr	$s4
	move	$s4, $a0
	lw	$t1, -4 ($fp)
	move	$s5, $t1
	bnez	$s5, dispatch_notvoid121
	la	$s6, str_const0
	move	$a0, $s6
	li	$s6, 471
	sw	$s6, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid121:
	move	$a0, $s5
	lw	$s6, 8 ($s5)
	lw	$s5, 44 ($s6)
	jalr	$s5
	move	$s5, $a0
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 36 ($s4)
	jalr	$s3
	move	$s3, $a0
	lw	$t1, -4 ($fp)
	move	$s4, $t1
	bnez	$s4, dispatch_notvoid122
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 471
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid122:
	move	$a0, $s4
	lw	$s5, 8 ($s4)
	lw	$s4, 48 ($s5)
	jalr	$s4
	move	$s4, $a0
	move	$a0, $s2
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s3, 8 ($s2)
	lw	$s2, 36 ($s3)
	jalr	$s2
	move	$s2, $a0
	lw	$t1, -4 ($fp)
	move	$s3, $t1
	bnez	$s3, dispatch_notvoid123
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 471
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid123:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 48 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 36 ($s2)
	jalr	$s1
	move	$s1, $a0
	lw	$t1, -4 ($fp)
	move	$s2, $t1
	bnez	$s2, dispatch_notvoid124
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 472
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid124:
	move	$a0, $s2
	lw	$s3, 8 ($s2)
	lw	$s2, 44 ($s3)
	jalr	$s2
	move	$s2, $a0
	move	$a0, $s0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s0)
	lw	$s0, 36 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s1, $t1
	bnez	$s1, dispatch_notvoid125
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 472
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid125:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 48 ($s2)
	jalr	$s1
	move	$s1, $a0
	lw	$t0, -32 ($fp)
	move	$a0, $t0
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$t0, -32 ($fp)
	lw	$s0, 8 ($t0)
	lw	$s1, 36 ($s0)
	jalr	$s1
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s1, $t1
	bnez	$s1, dispatch_notvoid126
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 472
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid126:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 40 ($s2)
	jalr	$s1
	move	$s1, $a0
	lw	$t0, -28 ($fp)
	move	$a0, $t0
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$t0, -28 ($fp)
	lw	$s0, 8 ($t0)
	lw	$s1, 36 ($s0)
	jalr	$s1
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s1, $t1
	bnez	$s1, dispatch_notvoid127
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 472
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid127:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 44 ($s2)
	jalr	$s1
	move	$s1, $a0
	lw	$t0, -24 ($fp)
	move	$a0, $t0
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$t0, -24 ($fp)
	lw	$s0, 8 ($t0)
	lw	$s1, 36 ($s0)
	jalr	$s1
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s1, $t1
	bnez	$s1, dispatch_notvoid128
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 472
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid128:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 40 ($s2)
	jalr	$s1
	move	$s1, $a0
	lw	$t0, -16 ($fp)
	move	$a0, $t0
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$t0, -16 ($fp)
	lw	$s0, 8 ($t0)
	lw	$s1, 36 ($s0)
	jalr	$s1
	move	$s0, $a0
	lw	$t0, -8 ($fp)
	move	$a0, $t0
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$t0, -8 ($fp)
	lw	$s0, 8 ($t0)
	lw	$s1, 64 ($s0)
	jalr	$s1
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$t0, $t1
	sw	$t0, -12 ($fp)
	lw	$t0, -12 ($fp)
	bnez	$t0, dispatch_notvoid129
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 473
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid129:
	lw	$t1, -4 ($fp)
	move	$t0, $t1
	sw	$t0, -20 ($fp)
	lw	$t0, -20 ($fp)
	bnez	$t0, dispatch_notvoid130
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 473
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid130:
	lw	$t1, -4 ($fp)
	move	$s0, $t1
	bnez	$s0, dispatch_notvoid131
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 473
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid131:
	lw	$t1, -4 ($fp)
	move	$s1, $t1
	bnez	$s1, dispatch_notvoid132
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 473
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid132:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 40 ($s2)
	jalr	$s1
	move	$s1, $a0
	lw	$t1, -4 ($fp)
	move	$s2, $t1
	bnez	$s2, dispatch_notvoid133
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 473
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid133:
	lw	$t1, -4 ($fp)
	move	$s3, $t1
	bnez	$s3, dispatch_notvoid134
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 473
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid134:
	move	$a0, $s3
	lw	$s4, 8 ($s3)
	lw	$s3, 44 ($s4)
	jalr	$s3
	move	$s3, $a0
	lw	$t1, -4 ($fp)
	move	$s4, $t1
	bnez	$s4, dispatch_notvoid135
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 473
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid135:
	move	$a0, $s4
	lw	$s5, 8 ($s4)
	lw	$s4, 48 ($s5)
	jalr	$s4
	move	$s4, $a0
	move	$a0, $s2
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s3, 8 ($s2)
	lw	$s2, 36 ($s3)
	jalr	$s2
	move	$s2, $a0
	move	$a0, $s0
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s0)
	lw	$s0, 36 ($s1)
	jalr	$s0
	move	$s0, $a0
	lw	$t1, -4 ($fp)
	move	$s1, $t1
	bnez	$s1, dispatch_notvoid136
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 473
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid136:
	lw	$t1, -4 ($fp)
	move	$s2, $t1
	bnez	$s2, dispatch_notvoid137
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 473
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid137:
	move	$a0, $s2
	lw	$s3, 8 ($s2)
	lw	$s2, 44 ($s3)
	jalr	$s2
	move	$s2, $a0
	lw	$t1, -4 ($fp)
	move	$s3, $t1
	bnez	$s3, dispatch_notvoid138
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 473
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid138:
	lw	$t1, -4 ($fp)
	move	$s4, $t1
	bnez	$s4, dispatch_notvoid139
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 473
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid139:
	move	$a0, $s4
	lw	$s5, 8 ($s4)
	lw	$s4, 48 ($s5)
	jalr	$s4
	move	$s4, $a0
	lw	$t1, -4 ($fp)
	move	$s5, $t1
	bnez	$s5, dispatch_notvoid140
	la	$s6, str_const0
	move	$a0, $s6
	li	$s6, 473
	sw	$s6, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid140:
	move	$a0, $s5
	lw	$s6, 8 ($s5)
	lw	$s5, 48 ($s6)
	jalr	$s5
	move	$s5, $a0
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 36 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 36 ($s2)
	jalr	$s1
	move	$s1, $a0
	lw	$t0, -20 ($fp)
	move	$a0, $t0
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$t0, -20 ($fp)
	lw	$s0, 8 ($t0)
	lw	$s1, 36 ($s0)
	jalr	$s1
	move	$s0, $a0
	lw	$t0, -12 ($fp)
	move	$a0, $t0
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$t0, -12 ($fp)
	lw	$s0, 8 ($t0)
	lw	$s1, 64 ($s0)
	jalr	$s1
	move	$s0, $a0
	li	$s0, 0
	move	$a0, $s0
	j	__Main.main_epilogue
__Main.main_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s6, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s5, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 40
	jr	$ra

# web count: 8
# VR0-[[0, 3), [3, 8), [8, 9)]-{0}-[1, 8] --> $s0
# VR1-[[1, 3), [3, 8), [8, 12)]-{1}-[2, 9, 11] --> $s1
# VR1-[[14, 16)]-{7}-[15] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s2
# VR2-[[5, 7)]-{3}-[6] --> $s2
# VR2-[[8, 11)]-{4}-[10] --> $s2
# VR2-[[11, 13)]-{5}-[12] --> $s0
# VR2-[[12, 14)]-{6}-[13] --> $s1
Variable.print_self:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid141
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 164
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid141:
	lw	$s2, 12 ($s0)
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s1)
	lw	$s1, 12 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__Variable.print_self_epilogue
__Variable.print_self_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 2
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s1
Variable.beta:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	move	$a0, $s1
	j	__Variable.beta_epilogue
__Variable.beta_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 7
# VR0-[[0, 7), [9, 10)]-{0}-[4, 9] --> $s0
# VR1-[[1, 4)]-{1}-[3] --> $s1
# VR2-[[2, 7), [7, 8)]-{2}-[7] --> $s2
# VR3-[[3, 6)]-{3}-[5] --> $s3
# VR3-[[5, 7)]-{5}-[6] --> $s1
# VR3-[[7, 9), [9, 10), [10, 11)]-{6, 7}-[10] --> $s1
# VR4-[[4, 6)]-{4}-[5] --> $s4
Variable.substitute:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($fp)
	lw	$s2, 8 ($fp)
	move	$s3, $s1
	move	$s4, $s0
	seq	$s1, $s3, $s4
	beqz	$s1, ite_false1
	move	$s1, $s2
	b	ite_end1
ite_false1:
	move	$s1, $s0
ite_end1:
	move	$a0, $s1
	j	__Variable.substitute_epilogue
__Variable.substitute_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 72
# VR0-[[0, 4), [4, 6), [6, 11), [11, 17), [17, 19), [19, 21), [21, 26), [26, 34), [34, 35), [35, 37), [37, 42), [42, 51), [51, 56), [56, 63), [63, 65), [65, 70), [70, 76), [76, 78), [78, 83), [83, 92), [92, 97), [97, 104), [104, 109), [109, 118), [118, 123), [123, 129), [130, 131)]-{0}-[102, 35, 116, 76, 128, 130, 31, 90] --> $s0
# VR1-[[1, 4)]-{1}-[3] --> $s1
# VR2-[[2, 3)]-{2}-[] --> $s2
# VR3-[[3, 4), [4, 6), [6, 11), [11, 17), [17, 19), [19, 21), [21, 26), [26, 34), [34, 35), [35, 37), [37, 42), [42, 50), [61, 63), [63, 64)]-{3, 33}-[19, 49, 4, 63] --> $s2
# VR3-[[144, 146)]-{74}-[145] --> $s0
# VR4-[[4, 6), [6, 11), [11, 13)]-{4}-[5, 11, 12] --> $s1
# VR4-[[15, 17)]-{9}-[16] --> $s1
# VR4-[[17, 19), [33, 34), [34, 35)]-{10, 19}-[34] --> $s1
# VR4-[[19, 21), [21, 26), [26, 28)]-{11}-[20, 27, 26] --> $s1
# VR4-[[30, 33)]-{16}-[32] --> $s1
# VR4-[[32, 34)]-{18}-[33] --> $s3
# VR4-[[35, 37), [37, 42), [42, 46)]-{20}-[36, 43, 45] --> $s1
# VR4-[[48, 49)]-{26}-[] --> $s1
# VR4-[[49, 51), [51, 56), [56, 58)]-{27}-[50, 57, 56] --> $s1
# VR4-[[60, 62)]-{32}-[61] --> $s1
# VR4-[[63, 65), [65, 70), [70, 72)]-{34}-[70, 71, 64] --> $s1
# VR4-[[74, 76)]-{39}-[75] --> $s1
# VR4-[[76, 78), [78, 83), [83, 87)]-{40}-[84, 86, 77] --> $s1
# VR4-[[89, 90)]-{46}-[] --> $s1
# VR4-[[90, 92), [92, 97), [97, 99)]-{47}-[98, 97, 91] --> $s1
# VR4-[[101, 102)]-{52}-[] --> $s1
# VR4-[[102, 104), [104, 109), [109, 113)]-{53}-[103, 112, 110] --> $s1
# VR4-[[115, 116)]-{59}-[] --> $s1
# VR4-[[116, 118), [118, 123), [123, 125)]-{60}-[117, 124, 123] --> $s1
# VR4-[[127, 128)]-{65}-[] --> $s1
# VR4-[[128, 130), [143, 144), [144, 145)]-{66, 73}-[144] --> $s1
# VR4-[[130, 132), [132, 137), [137, 141)]-{67}-[138, 140, 131] --> $s1
# VR5-[[6, 8)]-{5}-[7] --> $s3
# VR5-[[8, 10)]-{6}-[9] --> $s3
# VR5-[[12, 14)]-{7}-[13] --> $s3
# VR5-[[13, 15)]-{8}-[14] --> $s1
# VR5-[[21, 23)]-{12}-[22] --> $s3
# VR5-[[23, 25)]-{13}-[24] --> $s3
# VR5-[[27, 29)]-{14}-[28] --> $s3
# VR5-[[28, 30)]-{15}-[29] --> $s1
# VR5-[[31, 33)]-{17}-[32] --> $s4
# VR5-[[37, 39)]-{21}-[38] --> $s3
# VR5-[[39, 41)]-{22}-[40] --> $s3
# VR5-[[42, 45)]-{23}-[44] --> $s3
# VR5-[[45, 47)]-{24}-[46] --> $s3
# VR5-[[46, 48)]-{25}-[47] --> $s1
# VR5-[[51, 53)]-{28}-[52] --> $s2
# VR5-[[53, 55)]-{29}-[54] --> $s2
# VR5-[[57, 59)]-{30}-[58] --> $s2
# VR5-[[58, 60)]-{31}-[59] --> $s1
# VR5-[[65, 67)]-{35}-[66] --> $s2
# VR5-[[67, 69)]-{36}-[68] --> $s2
# VR5-[[71, 73)]-{37}-[72] --> $s2
# VR5-[[72, 74)]-{38}-[73] --> $s1
# VR5-[[78, 80)]-{41}-[79] --> $s2
# VR5-[[80, 82)]-{42}-[81] --> $s2
# VR5-[[83, 86)]-{43}-[85] --> $s2
# VR5-[[86, 88)]-{44}-[87] --> $s2
# VR5-[[87, 89)]-{45}-[88] --> $s1
# VR5-[[92, 94)]-{48}-[93] --> $s2
# VR5-[[94, 96)]-{49}-[95] --> $s2
# VR5-[[98, 100)]-{50}-[99] --> $s2
# VR5-[[99, 101)]-{51}-[100] --> $s1
# VR5-[[104, 106)]-{54}-[105] --> $s2
# VR5-[[106, 108)]-{55}-[107] --> $s2
# VR5-[[109, 112)]-{56}-[111] --> $s2
# VR5-[[112, 114)]-{57}-[113] --> $s2
# VR5-[[113, 115)]-{58}-[114] --> $s1
# VR5-[[118, 120)]-{61}-[119] --> $s2
# VR5-[[120, 122)]-{62}-[121] --> $s2
# VR5-[[124, 126)]-{63}-[125] --> $s2
# VR5-[[125, 127)]-{64}-[126] --> $s1
# VR5-[[132, 134)]-{68}-[133] --> $s0
# VR5-[[134, 136)]-{69}-[135] --> $s0
# VR5-[[137, 140)]-{70}-[139] --> $s0
# VR5-[[140, 142)]-{71}-[141] --> $s0
# VR5-[[141, 143)]-{72}-[142] --> $s1
Variable.gen_code:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($fp)
	lw	$s2, 8 ($fp)
	move	$s2, $s1
loop_start2:
	move	$s1, $s2
	bnez	$s1, dispatch_notvoid142
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 175
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid142:
	move	$a0, $s1
	lw	$s3, 8 ($s1)
	lw	$s1, 28 ($s3)
	jalr	$s1
	move	$s1, $a0
	beqz	$s1, ite_false2
	li	$s1, 0
	b	ite_end2
ite_false2:
	move	$s1, $s2
	bnez	$s1, dispatch_notvoid143
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 178
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid143:
	move	$a0, $s1
	lw	$s3, 8 ($s1)
	lw	$s1, 32 ($s3)
	jalr	$s1
	move	$s1, $a0
	move	$s4, $s0
	seq	$s3, $s1, $s4
	li	$t0, 1
	sub	$s1, $t0, $s3
ite_end2:
	beqz	$s1, loop_end2
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid144
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 180
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid144:
	la	$s3, str_const7
	move	$a0, $s1
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s3, 8 ($s1)
	lw	$s1, 12 ($s3)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s2
	bnez	$s1, dispatch_notvoid145
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 181
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid145:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 36 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s2, $s1
	b	loop_start2
loop_end2:
	move	$s1, $s2
	bnez	$s1, dispatch_notvoid146
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 184
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid146:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 28 ($s2)
	jalr	$s1
	move	$s1, $a0
	beqz	$s1, ite_false3
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid147
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 185
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid147:
	la	$s2, str_const8
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid148
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 186
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid148:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 28 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid149
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 187
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid149:
	la	$s2, str_const1
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid150
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 188
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid150:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 0 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	b	ite_end3
ite_false3:
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid151
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 192
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid151:
	la	$s0, str_const9
	move	$a0, $s1
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s1)
	lw	$s1, 12 ($s0)
	jalr	$s1
	move	$s1, $a0
ite_end3:
	move	$s0, $s1
	move	$a0, $s0
	j	__Variable.gen_code_epilogue
__Variable.gen_code_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 4
# VR0-[[0, 5)]-{0}-[3, 4] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s1
# VR2-[[2, 4)]-{2}-[3] --> $s2
# VR2-[[4, 6)]-{3}-[5] --> $s1
Variable.init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 8 ($fp)
	move	$s2, $s1
	sw	$s2, 12 ($s0)
	move	$s1, $s0
	move	$a0, $s1
	j	__Variable.init_epilogue
__Variable.init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 12
	jr	$ra

# web count: 28
# VR0-[[0, 3), [3, 8), [8, 17), [17, 22), [22, 29), [29, 34), [34, 43), [43, 48), [48, 54)]-{0}-[1, 53, 27, 41, 15] --> $s0
# VR1-[[1, 3), [3, 8), [8, 12)]-{1}-[2, 9, 11] --> $s1
# VR1-[[14, 15)]-{7}-[] --> $s1
# VR1-[[15, 17), [17, 22), [22, 24)]-{8}-[16, 23, 22] --> $s1
# VR1-[[26, 27)]-{13}-[] --> $s1
# VR1-[[27, 29), [29, 34), [34, 38)]-{14}-[35, 37, 28] --> $s1
# VR1-[[40, 41)]-{20}-[] --> $s1
# VR1-[[41, 43), [43, 48), [48, 50)]-{21}-[49, 48, 42] --> $s1
# VR1-[[52, 53)]-{26}-[] --> $s1
# VR1-[[53, 55)]-{27}-[54] --> $s1
# VR2-[[3, 5)]-{2}-[4] --> $s2
# VR2-[[5, 7)]-{3}-[6] --> $s2
# VR2-[[8, 11)]-{4}-[10] --> $s2
# VR2-[[11, 13)]-{5}-[12] --> $s2
# VR2-[[12, 14)]-{6}-[13] --> $s1
# VR2-[[17, 19)]-{9}-[18] --> $s2
# VR2-[[19, 21)]-{10}-[20] --> $s2
# VR2-[[23, 25)]-{11}-[24] --> $s2
# VR2-[[24, 26)]-{12}-[25] --> $s1
# VR2-[[29, 31)]-{15}-[30] --> $s2
# VR2-[[31, 33)]-{16}-[32] --> $s2
# VR2-[[34, 37)]-{17}-[36] --> $s2
# VR2-[[37, 39)]-{18}-[38] --> $s2
# VR2-[[38, 40)]-{19}-[39] --> $s1
# VR2-[[43, 45)]-{22}-[44] --> $s2
# VR2-[[45, 47)]-{23}-[46] --> $s2
# VR2-[[49, 51)]-{24}-[50] --> $s2
# VR2-[[50, 52)]-{25}-[51] --> $s1
Lambda.print_self:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid152
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 215
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid152:
	la	$s2, str_const10
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	lw	$s1, 12 ($s0)
	bnez	$s1, dispatch_notvoid153
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 216
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid153:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 28 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid154
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 217
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid154:
	la	$s2, str_const11
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	lw	$s1, 16 ($s0)
	bnez	$s1, dispatch_notvoid155
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 218
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid155:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 28 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	move	$a0, $s1
	j	__Lambda.print_self_epilogue
__Lambda.print_self_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 2
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s1
Lambda.beta:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	move	$a0, $s1
	j	__Lambda.beta_epilogue
__Lambda.beta_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 26
# VR0-[[0, 7), [7, 8), [9, 11), [11, 16), [16, 32), [32, 37), [37, 38)]-{0}-[4, 7, 37, 9] --> $s0
# VR1-[[1, 7), [9, 11), [11, 16), [16, 17)]-{1}-[16, 3] --> $s1
# VR2-[[2, 7), [9, 11), [11, 16), [16, 18)]-{2}-[17] --> $s2
# VR3-[[3, 6)]-{3}-[5] --> $s3
# VR3-[[5, 7)]-{5}-[6] --> $s4
# VR3-[[7, 9), [47, 48), [48, 49)]-{6, 26}-[48] --> $s1
# VR3-[[9, 11), [11, 16), [16, 22)]-{7}-[18, 21, 10] --> $s3
# VR3-[[24, 32), [32, 37), [37, 39)]-{14}-[38] --> $s1
# VR4-[[4, 6)]-{4}-[5] --> $s5
# VR4-[[11, 13)]-{8}-[12] --> $s4
# VR4-[[13, 15)]-{9}-[14] --> $s4
# VR4-[[16, 20)]-{10}-[19] --> $s4
# VR4-[[21, 23)]-{12}-[22] --> $s1
# VR4-[[22, 24)]-{13}-[23] --> $s2
# VR4-[[25, 27)]-{15}-[26] --> $s2
# VR4-[[28, 31)]-{16}-[30] --> $s2
# VR4-[[46, 48)]-{25}-[47] --> $s0
# VR5-[[17, 21)]-{11}-[20] --> $s1
# VR5-[[30, 32), [32, 37), [37, 43)]-{17}-[39, 42, 31] --> $s3
# VR5-[[45, 47)]-{24}-[46] --> $s1
# VR6-[[32, 34)]-{18}-[33] --> $s2
# VR6-[[34, 36)]-{19}-[35] --> $s2
# VR6-[[37, 41)]-{20}-[40] --> $s2
# VR6-[[42, 44)]-{22}-[43] --> $s0
# VR6-[[43, 45)]-{23}-[44] --> $s1
# VR7-[[38, 42)]-{21}-[41] --> $s0
Lambda.substitute:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($fp)
	lw	$s2, 8 ($fp)
	move	$s3, $s1
	lw	$s5, 12 ($s0)
	seq	$s4, $s3, $s5
	beqz	$s4, ite_false4
	move	$s1, $s0
	b	ite_end4
ite_false4:
	lw	$s3, 16 ($s0)
	bnez	$s3, dispatch_notvoid156
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 234
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid156:
	move	$s4, $s1
	move	$s1, $s2
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s3)
	lw	$s2, 36 ($s1)
	jalr	$s2
	move	$s1, $a0
	la	$s2, Lambda_protObj
	move	$a0, $s2
	jal	Object.copy
	move	$s2, $a0
	jal	Lambda_init
	move	$s3, $s2
	bnez	$s3, dispatch_notvoid157
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 236
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid157:
	lw	$s2, 12 ($s0)
	move	$s0, $s1
	move	$a0, $s3
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s3)
	lw	$s1, 44 ($s0)
	jalr	$s1
	move	$s1, $a0
	move	$s0, $s1
	move	$s1, $s0
ite_end4:
	move	$a0, $s1
	j	__Lambda.substitute_epilogue
__Lambda.substitute_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s5, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 55
# VR0-[[0, 5), [5, 10), [10, 19), [19, 24), [24, 26), [26, 31), [31, 54), [54, 59), [59, 68), [68, 73), [73, 79), [79, 81), [81, 86), [86, 94), [94, 96), [96, 101), [101, 108), [108, 109)]-{0}-[17, 32, 3, 52, 108, 79, 94] --> $s0
# VR1-[[1, 5), [5, 10), [10, 19), [19, 24), [24, 26), [26, 31), [31, 54), [54, 59), [59, 67)]-{1}-[66, 31] --> $s1
# VR2-[[2, 5), [5, 10), [10, 19), [19, 24), [24, 25)]-{2}-[24] --> $s2
# VR3-[[3, 5), [5, 10), [10, 14)]-{3}-[4, 11, 13] --> $s3
# VR3-[[16, 17)]-{9}-[] --> $s3
# VR3-[[17, 19), [19, 24), [24, 26), [26, 31), [31, 49)]-{10}-[18, 48, 46] --> $s3
# VR3-[[51, 52)]-{26}-[] --> $s2
# VR3-[[52, 54), [54, 59), [59, 63)]-{27}-[53, 62, 60] --> $s2
# VR3-[[65, 66)]-{33}-[] --> $s2
# VR3-[[66, 68), [68, 73), [73, 75)]-{34}-[67, 73, 74] --> $s2
# VR3-[[77, 79)]-{39}-[78] --> $s1
# VR3-[[79, 81), [81, 86), [86, 90)]-{40}-[87, 80, 89] --> $s1
# VR3-[[92, 93)]-{46}-[] --> $s1
# VR3-[[94, 96), [96, 101), [101, 105)]-{47}-[102, 95, 104] --> $s1
# VR3-[[107, 108)]-{53}-[] --> $s1
# VR3-[[108, 110)]-{54}-[109] --> $s1
# VR4-[[5, 7)]-{4}-[6] --> $s4
# VR4-[[7, 9)]-{5}-[8] --> $s4
# VR4-[[10, 13)]-{6}-[12] --> $s4
# VR4-[[13, 15)]-{7}-[14] --> $s4
# VR4-[[14, 16)]-{8}-[15] --> $s3
# VR4-[[19, 21)]-{11}-[20] --> $s4
# VR4-[[21, 23)]-{12}-[22] --> $s4
# VR4-[[24, 26), [26, 31), [31, 37)]-{13}-[33, 36, 25] --> $s4
# VR4-[[39, 45)]-{20}-[44] --> $s2
# VR4-[[45, 48)]-{23}-[47] --> $s2
# VR4-[[48, 50)]-{24}-[49] --> $s2
# VR4-[[49, 51)]-{25}-[50] --> $s3
# VR4-[[54, 56)]-{28}-[55] --> $s3
# VR4-[[56, 58)]-{29}-[57] --> $s3
# VR4-[[59, 62)]-{30}-[61] --> $s3
# VR4-[[62, 64)]-{31}-[63] --> $s3
# VR4-[[63, 65)]-{32}-[64] --> $s2
# VR4-[[68, 70)]-{35}-[69] --> $s1
# VR4-[[70, 72)]-{36}-[71] --> $s1
# VR4-[[74, 76)]-{37}-[75] --> $s1
# VR4-[[75, 77)]-{38}-[76] --> $s2
# VR4-[[81, 83)]-{41}-[82] --> $s2
# VR4-[[83, 85)]-{42}-[84] --> $s2
# VR4-[[86, 89)]-{43}-[88] --> $s2
# VR4-[[89, 91)]-{44}-[90] --> $s2
# VR4-[[90, 92)]-{45}-[91] --> $s1
# VR4-[[96, 98)]-{48}-[97] --> $s2
# VR4-[[98, 100)]-{49}-[99] --> $s2
# VR4-[[101, 104)]-{50}-[103] --> $s2
# VR4-[[104, 106)]-{51}-[105] --> $s2
# VR4-[[105, 107)]-{52}-[106] --> $s1
# VR5-[[26, 28)]-{14}-[27] --> $s2
# VR5-[[28, 30)]-{15}-[29] --> $s2
# VR5-[[31, 35)]-{16}-[34] --> $s2
# VR5-[[36, 38)]-{18}-[37] --> $s2
# VR5-[[37, 39)]-{19}-[38] --> $s4
# VR5-[[40, 42)]-{21}-[41] --> $s4
# VR5-[[43, 46)]-{22}-[44, 45] --> $s4
# VR6-[[32, 36)]-{17}-[35] --> $s5
Lambda.gen_code:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($fp)
	lw	$s2, 8 ($fp)
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid158
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 242
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid158:
	la	$s4, str_const12
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 12 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid159
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 243
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid159:
	move	$s4, $s2
	bnez	$s4, dispatch_notvoid160
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 243
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid160:
	move	$s2, $s1
	move	$s5, $s0
	move	$a0, $s4
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s4)
	lw	$s4, 32 ($s2)
	jalr	$s4
	move	$s2, $a0
	la	$s4, Int_protObj
	move	$a0, $s4
	jal	Object.copy
	move	$s4, $a0
	sw	$s2, 12 ($s4)
	move	$s2, $s4
	move	$a0, $s3
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s3)
	lw	$s3, 16 ($s2)
	jalr	$s3
	move	$s2, $a0
	move	$s2, $s0
	bnez	$s2, dispatch_notvoid161
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 244
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid161:
	la	$s3, str_const13
	move	$a0, $s2
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s3, 8 ($s2)
	lw	$s2, 12 ($s3)
	jalr	$s2
	move	$s2, $a0
	move	$s2, $s1
	bnez	$s2, dispatch_notvoid162
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 245
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid162:
	move	$a0, $s2
	lw	$s1, 8 ($s2)
	lw	$s2, 28 ($s1)
	jalr	$s2
	move	$s1, $a0
	beqz	$s1, ite_false5
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid163
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 246
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid163:
	la	$s2, str_const14
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	b	ite_end5
ite_false5:
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid164
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 248
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid164:
	la	$s2, str_const15
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
ite_end5:
	move	$s1, $s0
	move	$a0, $s1
	j	__Lambda.gen_code_epilogue
__Lambda.gen_code_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s5, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 6
# VR0-[[0, 8)]-{0}-[4, 6, 7] --> $s0
# VR1-[[1, 4)]-{1}-[3] --> $s1
# VR2-[[2, 6)]-{2}-[5] --> $s2
# VR3-[[3, 5)]-{3}-[4] --> $s3
# VR3-[[5, 7)]-{4}-[6] --> $s1
# VR3-[[7, 9)]-{5}-[8] --> $s1
Lambda.init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($fp)
	lw	$s2, 8 ($fp)
	move	$s3, $s1
	sw	$s3, 12 ($s0)
	move	$s1, $s2
	sw	$s1, 16 ($s0)
	move	$s1, $s0
	move	$a0, $s1
	j	__Lambda.init_epilogue
__Lambda.init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 10
# VR0-[[0, 4), [4, 9), [9, 10)]-{0}-[2, 9] --> $s0
# VR1-[[1, 4), [4, 9), [9, 11)]-{1}-[10] --> $s1
# VR2-[[2, 4), [4, 9), [9, 15)]-{2}-[3, 11, 14] --> $s2
# VR2-[[17, 19)]-{9}-[18] --> $s0
# VR3-[[4, 6)]-{3}-[5] --> $s3
# VR3-[[6, 8)]-{4}-[7] --> $s3
# VR3-[[9, 13)]-{5}-[12] --> $s3
# VR3-[[14, 16)]-{7}-[15] --> $s0
# VR3-[[15, 17)]-{8}-[16] --> $s1
# VR4-[[10, 14)]-{6}-[13] --> $s0
Lambda.apply:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 8 ($fp)
	lw	$s2, 16 ($s0)
	bnez	$s2, dispatch_notvoid165
	la	$s3, str_const0
	move	$a0, $s3
	li	$s3, 226
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid165:
	lw	$s3, 12 ($s0)
	move	$s0, $s1
	move	$a0, $s2
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s2)
	lw	$s1, 36 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__Lambda.apply_epilogue
__Lambda.apply_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 12
	jr	$ra

# web count: 94
# VR0-[[0, 6), [6, 11), [11, 20), [20, 25), [25, 40), [40, 45), [45, 54), [54, 59), [59, 68), [68, 73), [73, 82), [82, 87), [87, 102), [102, 107), [107, 116), [116, 121), [121, 130), [130, 135), [135, 137), [137, 142), [142, 159), [159, 164), [164, 172)]-{0}-[171, 100, 18, 4, 38, 80, 114, 157, 66, 52, 142, 128] --> $s0
# VR1-[[1, 6), [6, 11), [11, 20), [20, 25), [25, 40), [40, 45), [45, 54), [54, 59), [59, 68), [68, 73), [73, 82), [82, 87), [87, 88)]-{1}-[87, 25] --> $s1
# VR2-[[2, 6), [6, 11), [11, 20), [20, 25), [25, 40), [40, 45), [45, 54), [54, 59), [59, 68), [68, 73), [73, 82), [82, 87), [87, 102), [102, 107), [107, 116), [116, 121), [121, 130), [130, 135), [135, 136)]-{2}-[135] --> $s2
# VR3-[[3, 6), [6, 11), [11, 20), [20, 25), [25, 40), [40, 45), [45, 54), [54, 59), [59, 68), [68, 73), [73, 82), [82, 87), [87, 102), [102, 107), [107, 116), [116, 121), [121, 130), [130, 135), [135, 137), [137, 142), [142, 150)]-{3}-[149] --> $s3
# VR4-[[4, 6), [6, 11), [11, 15)]-{4}-[5, 12, 14] --> $s4
# VR4-[[17, 18)]-{10}-[] --> $s4
# VR4-[[18, 20), [20, 25), [25, 35)]-{11}-[34, 19, 32] --> $s4
# VR4-[[37, 38)]-{20}-[] --> $s4
# VR4-[[38, 40), [40, 45), [45, 49)]-{21}-[48, 39, 46] --> $s4
# VR4-[[51, 52)]-{27}-[] --> $s4
# VR4-[[52, 54), [54, 59), [59, 63)]-{28}-[53, 62, 60] --> $s4
# VR4-[[65, 66)]-{34}-[] --> $s4
# VR4-[[66, 68), [68, 73), [73, 77)]-{35}-[67, 76, 74] --> $s4
# VR4-[[79, 80)]-{41}-[] --> $s4
# VR4-[[80, 82), [82, 87), [87, 97)]-{42}-[81, 96, 94] --> $s4
# VR4-[[99, 100)]-{51}-[] --> $s1
# VR4-[[100, 102), [102, 107), [107, 111)]-{52}-[101, 110, 108] --> $s1
# VR4-[[113, 114)]-{58}-[] --> $s1
# VR4-[[114, 116), [116, 121), [121, 125)]-{59}-[115, 124, 122] --> $s1
# VR4-[[127, 128)]-{65}-[] --> $s1
# VR4-[[128, 130), [130, 135), [135, 137), [137, 142), [142, 154)]-{66}-[153, 129, 150] --> $s1
# VR4-[[156, 157)]-{79}-[] --> $s1
# VR4-[[157, 159), [159, 164), [164, 168)]-{80}-[158, 167, 165] --> $s1
# VR4-[[170, 171)]-{86}-[] --> $s1
# VR4-[[171, 173), [173, 178), [178, 182)]-{87}-[172, 179, 181] --> $s1
# VR4-[[184, 186)]-{93}-[185] --> $s0
# VR5-[[6, 8)]-{5}-[7] --> $s5
# VR5-[[8, 10)]-{6}-[9] --> $s5
# VR5-[[11, 14)]-{7}-[13] --> $s5
# VR5-[[14, 16)]-{8}-[15] --> $s5
# VR5-[[15, 17)]-{9}-[16] --> $s4
# VR5-[[20, 22)]-{12}-[21] --> $s5
# VR5-[[22, 24)]-{13}-[23] --> $s5
# VR5-[[25, 31)]-{14}-[30] --> $s5
# VR5-[[31, 34)]-{17}-[33] --> $s5
# VR5-[[34, 36)]-{18}-[35] --> $s5
# VR5-[[35, 37)]-{19}-[36] --> $s4
# VR5-[[40, 42)]-{22}-[41] --> $s5
# VR5-[[42, 44)]-{23}-[43] --> $s5
# VR5-[[45, 48)]-{24}-[47] --> $s5
# VR5-[[48, 50)]-{25}-[49] --> $s5
# VR5-[[49, 51)]-{26}-[50] --> $s4
# VR5-[[54, 56)]-{29}-[55] --> $s5
# VR5-[[56, 58)]-{30}-[57] --> $s5
# VR5-[[59, 62)]-{31}-[61] --> $s5
# VR5-[[62, 64)]-{32}-[63] --> $s5
# VR5-[[63, 65)]-{33}-[64] --> $s4
# VR5-[[68, 70)]-{36}-[69] --> $s5
# VR5-[[70, 72)]-{37}-[71] --> $s5
# VR5-[[73, 76)]-{38}-[75] --> $s5
# VR5-[[76, 78)]-{39}-[77] --> $s5
# VR5-[[77, 79)]-{40}-[78] --> $s4
# VR5-[[82, 84)]-{43}-[83] --> $s5
# VR5-[[84, 86)]-{44}-[85] --> $s5
# VR5-[[87, 93)]-{45}-[92] --> $s5
# VR5-[[93, 96)]-{48}-[95] --> $s1
# VR5-[[96, 98)]-{49}-[97] --> $s1
# VR5-[[97, 99)]-{50}-[98] --> $s4
# VR5-[[102, 104)]-{53}-[103] --> $s4
# VR5-[[104, 106)]-{54}-[105] --> $s4
# VR5-[[107, 110)]-{55}-[109] --> $s4
# VR5-[[110, 112)]-{56}-[111] --> $s4
# VR5-[[111, 113)]-{57}-[112] --> $s1
# VR5-[[116, 118)]-{60}-[117] --> $s4
# VR5-[[118, 120)]-{61}-[119] --> $s4
# VR5-[[121, 124)]-{62}-[123] --> $s4
# VR5-[[124, 126)]-{63}-[125] --> $s4
# VR5-[[125, 127)]-{64}-[126] --> $s1
# VR5-[[130, 132)]-{67}-[131] --> $s4
# VR5-[[132, 134)]-{68}-[133] --> $s4
# VR5-[[135, 137), [137, 142), [142, 146)]-{69}-[136, 143, 145] --> $s4
# VR5-[[148, 152)]-{75}-[151] --> $s2
# VR5-[[153, 155)]-{77}-[154] --> $s2
# VR5-[[154, 156)]-{78}-[155] --> $s1
# VR5-[[159, 161)]-{81}-[160] --> $s2
# VR5-[[161, 163)]-{82}-[162] --> $s2
# VR5-[[164, 167)]-{83}-[166] --> $s2
# VR5-[[167, 169)]-{84}-[168] --> $s2
# VR5-[[168, 170)]-{85}-[169] --> $s1
# VR5-[[173, 175)]-{88}-[174] --> $s0
# VR5-[[175, 177)]-{89}-[176] --> $s0
# VR5-[[178, 181)]-{90}-[180] --> $s0
# VR5-[[181, 183)]-{91}-[182] --> $s0
# VR5-[[182, 184)]-{92}-[183] --> $s1
# VR6-[[26, 28)]-{15}-[27] --> $s6
# VR6-[[29, 32)]-{16}-[31, 30] --> $s6
# VR6-[[88, 90)]-{46}-[89] --> $s1
# VR6-[[91, 94)]-{47}-[93, 92] --> $s6
# VR6-[[137, 139)]-{70}-[138] --> $s2
# VR6-[[139, 141)]-{71}-[140] --> $s2
# VR6-[[142, 145)]-{72}-[144] --> $s2
# VR6-[[145, 147)]-{73}-[146] --> $s2
# VR6-[[146, 148)]-{74}-[147] --> $s4
# VR6-[[149, 153)]-{76}-[152] --> $s4
Lambda.gen_closure_code:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s6, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 16 ($fp)
	lw	$s2, 12 ($fp)
	lw	$s3, 8 ($fp)
	move	$s4, $s0
	bnez	$s4, dispatch_notvoid166
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 256
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid166:
	la	$s5, str_const16
	move	$a0, $s4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s5, 8 ($s4)
	lw	$s4, 12 ($s5)
	jalr	$s4
	move	$s4, $a0
	move	$s4, $s0
	bnez	$s4, dispatch_notvoid167
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 257
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid167:
	move	$s5, $s1
	la	$s6, Int_protObj
	move	$a0, $s6
	jal	Object.copy
	move	$s6, $a0
	sw	$s5, 12 ($s6)
	move	$s5, $s6
	move	$a0, $s4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s5, 8 ($s4)
	lw	$s4, 16 ($s5)
	jalr	$s4
	move	$s4, $a0
	move	$s4, $s0
	bnez	$s4, dispatch_notvoid168
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 258
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid168:
	la	$s5, str_const17
	move	$a0, $s4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s5, 8 ($s4)
	lw	$s4, 12 ($s5)
	jalr	$s4
	move	$s4, $a0
	move	$s4, $s0
	bnez	$s4, dispatch_notvoid169
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 259
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid169:
	la	$s5, str_const18
	move	$a0, $s4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s5, 8 ($s4)
	lw	$s4, 12 ($s5)
	jalr	$s4
	move	$s4, $a0
	move	$s4, $s0
	bnez	$s4, dispatch_notvoid170
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 260
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid170:
	la	$s5, str_const19
	move	$a0, $s4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s5, 8 ($s4)
	lw	$s4, 12 ($s5)
	jalr	$s4
	move	$s4, $a0
	move	$s4, $s0
	bnez	$s4, dispatch_notvoid171
	la	$s5, str_const0
	move	$a0, $s5
	li	$s5, 261
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid171:
	move	$s5, $s1
	la	$s1, Int_protObj
	move	$a0, $s1
	jal	Object.copy
	move	$s6, $a0
	sw	$s5, 12 ($s6)
	move	$s1, $s6
	move	$a0, $s4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s4)
	lw	$s4, 16 ($s1)
	jalr	$s4
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid172
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 262
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid172:
	la	$s4, str_const20
	move	$a0, $s1
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s1)
	lw	$s1, 12 ($s4)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid173
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 263
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid173:
	la	$s4, str_const21
	move	$a0, $s1
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s1)
	lw	$s1, 12 ($s4)
	jalr	$s1
	move	$s1, $a0
	lw	$s1, 16 ($s0)
	bnez	$s1, dispatch_notvoid174
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 264
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid174:
	move	$s4, $s2
	bnez	$s4, dispatch_notvoid175
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 264
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid175:
	lw	$s2, 12 ($s0)
	move	$a0, $s4
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s4)
	lw	$s4, 40 ($s2)
	jalr	$s4
	move	$s2, $a0
	move	$s4, $s3
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 40 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid176
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 265
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid176:
	la	$s2, str_const22
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid177
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 266
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid177:
	la	$s0, str_const23
	move	$a0, $s1
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s1)
	lw	$s1, 12 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__Lambda.gen_closure_code_epilogue
__Lambda.gen_closure_code_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s6, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s5, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 20
	jr	$ra

# web count: 35
# VR0-[[0, 3), [3, 8), [8, 17), [17, 22), [22, 29), [29, 34), [34, 43), [43, 48), [48, 55), [55, 60), [60, 68)]-{0}-[1, 53, 67, 27, 41, 15] --> $s0
# VR1-[[1, 3), [3, 8), [8, 12)]-{1}-[2, 9, 11] --> $s1
# VR1-[[14, 15)]-{7}-[] --> $s1
# VR1-[[15, 17), [17, 22), [22, 24)]-{8}-[16, 23, 22] --> $s1
# VR1-[[26, 27)]-{13}-[] --> $s1
# VR1-[[27, 29), [29, 34), [34, 38)]-{14}-[35, 37, 28] --> $s1
# VR1-[[40, 41)]-{20}-[] --> $s1
# VR1-[[41, 43), [43, 48), [48, 50)]-{21}-[49, 48, 42] --> $s1
# VR1-[[52, 53)]-{26}-[] --> $s1
# VR1-[[53, 55), [55, 60), [60, 64)]-{27}-[54, 63, 61] --> $s1
# VR1-[[66, 67)]-{33}-[] --> $s1
# VR1-[[67, 69)]-{34}-[68] --> $s1
# VR2-[[3, 5)]-{2}-[4] --> $s2
# VR2-[[5, 7)]-{3}-[6] --> $s2
# VR2-[[8, 11)]-{4}-[10] --> $s2
# VR2-[[11, 13)]-{5}-[12] --> $s2
# VR2-[[12, 14)]-{6}-[13] --> $s1
# VR2-[[17, 19)]-{9}-[18] --> $s2
# VR2-[[19, 21)]-{10}-[20] --> $s2
# VR2-[[23, 25)]-{11}-[24] --> $s2
# VR2-[[24, 26)]-{12}-[25] --> $s1
# VR2-[[29, 31)]-{15}-[30] --> $s2
# VR2-[[31, 33)]-{16}-[32] --> $s2
# VR2-[[34, 37)]-{17}-[36] --> $s2
# VR2-[[37, 39)]-{18}-[38] --> $s2
# VR2-[[38, 40)]-{19}-[39] --> $s1
# VR2-[[43, 45)]-{22}-[44] --> $s2
# VR2-[[45, 47)]-{23}-[46] --> $s2
# VR2-[[49, 51)]-{24}-[50] --> $s2
# VR2-[[50, 52)]-{25}-[51] --> $s1
# VR2-[[55, 57)]-{28}-[56] --> $s2
# VR2-[[57, 59)]-{29}-[58] --> $s2
# VR2-[[60, 63)]-{30}-[62] --> $s2
# VR2-[[63, 65)]-{31}-[64] --> $s2
# VR2-[[64, 66)]-{32}-[65] --> $s1
App.print_self:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid178
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 288
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid178:
	la	$s2, str_const24
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	lw	$s1, 12 ($s0)
	bnez	$s1, dispatch_notvoid179
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 289
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid179:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 28 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid180
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 290
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid180:
	la	$s2, str_const25
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	lw	$s1, 16 ($s0)
	bnez	$s1, dispatch_notvoid181
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 291
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid181:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 28 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid182
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 292
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid182:
	la	$s2, str_const26
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	move	$a0, $s1
	j	__App.print_self_epilogue
__App.print_self_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 32
# VR0-[[0, 3), [3, 8), [8, 11), [11, 13), [13, 18), [18, 19), [26, 28), [28, 30), [30, 32), [32, 37), [37, 49), [49, 54), [54, 56)]-{0}-[1, 18, 55, 30] --> $s0
# VR1-[[1, 3), [3, 8), [8, 11), [11, 12), [26, 28), [28, 30), [66, 67)]-{1}-[2, 66, 8, 11] --> $s1
# VR1-[[68, 70)]-{33}-[69] --> $s0
# VR2-[[3, 5)]-{2}-[4] --> $s2
# VR2-[[5, 7)]-{3}-[6] --> $s2
# VR2-[[8, 11), [24, 26), [26, 28), [28, 30), [64, 66), [66, 68), [68, 69)]-{4, 12, 32}-[68, 9, 26, 28] --> $s2
# VR2-[[11, 13), [13, 18), [18, 22)]-{6}-[19, 21, 12] --> $s2
# VR2-[[30, 32), [32, 37), [37, 39)]-{15}-[38, 37, 31] --> $s1
# VR2-[[41, 49), [49, 54), [54, 55)]-{20}-[54] --> $s1
# VR3-[[9, 11)]-{5}-[10] --> $s3
# VR3-[[13, 15)]-{7}-[14] --> $s1
# VR3-[[15, 17)]-{8}-[16] --> $s1
# VR3-[[18, 21)]-{9}-[20] --> $s1
# VR3-[[21, 23)]-{10}-[22] --> $s0
# VR3-[[22, 24)]-{11}-[23] --> $s1
# VR3-[[26, 28)]-{13}-[27] --> $s3
# VR3-[[28, 30)]-{14}-[29] --> $s3
# VR3-[[32, 34)]-{16}-[33] --> $s2
# VR3-[[34, 36)]-{17}-[35] --> $s2
# VR3-[[38, 40)]-{18}-[39] --> $s2
# VR3-[[39, 41)]-{19}-[40] --> $s1
# VR3-[[42, 44)]-{21}-[43] --> $s2
# VR3-[[45, 48)]-{22}-[47] --> $s2
# VR3-[[63, 65)]-{31}-[64] --> $s0
# VR4-[[47, 49), [49, 54), [54, 60)]-{23}-[48, 59, 56] --> $s3
# VR4-[[62, 64)]-{30}-[63] --> $s1
# VR5-[[49, 51)]-{24}-[50] --> $s2
# VR5-[[51, 53)]-{25}-[52] --> $s2
# VR5-[[54, 58)]-{26}-[57] --> $s2
# VR5-[[59, 61)]-{28}-[60] --> $s0
# VR5-[[60, 62)]-{29}-[61] --> $s1
# VR6-[[55, 59)]-{27}-[58] --> $s1
App.beta:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($s0)
	bnez	$s1, case0_notvoid
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 298
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_case_handler
case0_notvoid:
	lw	$s2, 0 ($s1)
case0_tag13:
	seq	$s3, $s2, 13
	beqz	$s3, case0_tag9
	move	$s2, $s1
	bnez	$s2, dispatch_notvoid183
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 299
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid183:
	lw	$s1, 16 ($s0)
	move	$a0, $s2
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s2)
	lw	$s1, 48 ($s0)
	jalr	$s1
	move	$s2, $a0
	b	case0_end
case0_tag9:
	slt	$s3, $s2, 9
	bnez	$s3, case0_error
	li	$t0, 14
	slt	$s3, $t0, $s2
	bnez	$s3, case0_error
	lw	$s1, 12 ($s0)
	bnez	$s1, dispatch_notvoid184
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 301
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid184:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 32 ($s2)
	jalr	$s1
	move	$s1, $a0
	la	$s2, App_protObj
	move	$a0, $s2
	jal	Object.copy
	move	$s2, $a0
	jal	App_init
	move	$s3, $s2
	bnez	$s3, dispatch_notvoid185
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 303
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid185:
	move	$s2, $s1
	lw	$s1, 16 ($s0)
	move	$a0, $s3
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s3)
	lw	$s1, 44 ($s0)
	jalr	$s1
	move	$s1, $a0
	move	$s0, $s1
	move	$s2, $s0
	b	case0_end
case0_error:
	move	$a0, $s1
	jal	_case_abort
case0_end:
	move	$s0, $s2
	move	$a0, $s0
	j	__App.beta_epilogue
__App.beta_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 32
# VR0-[[0, 5), [5, 10), [10, 20)]-{0}-[19, 3] --> $s0
# VR1-[[1, 5), [5, 10), [10, 21), [21, 26), [26, 27)]-{1}-[10, 26] --> $s1
# VR2-[[2, 5), [5, 10), [10, 21), [21, 26), [26, 28)]-{2}-[27, 11] --> $s2
# VR3-[[3, 5), [5, 10), [10, 16)]-{3}-[4, 12, 15] --> $s3
# VR3-[[18, 21), [21, 26), [26, 42), [42, 47), [47, 48)]-{10}-[47] --> $s3
# VR3-[[58, 60)]-{31}-[59] --> $s0
# VR4-[[5, 7)]-{4}-[6] --> $s4
# VR4-[[7, 9)]-{5}-[8] --> $s4
# VR4-[[10, 14)]-{6}-[13] --> $s4
# VR4-[[15, 17)]-{8}-[16] --> $s4
# VR4-[[16, 18)]-{9}-[17] --> $s3
# VR4-[[19, 21), [21, 26), [26, 32)]-{11}-[20, 28, 31] --> $s4
# VR4-[[34, 42), [42, 47), [47, 49)]-{18}-[48] --> $s0
# VR4-[[57, 59)]-{30}-[58] --> $s1
# VR5-[[11, 15)]-{7}-[14] --> $s5
# VR5-[[21, 23)]-{12}-[22] --> $s0
# VR5-[[23, 25)]-{13}-[24] --> $s0
# VR5-[[26, 30)]-{14}-[29] --> $s0
# VR5-[[31, 33)]-{16}-[32] --> $s0
# VR5-[[32, 34)]-{17}-[33] --> $s1
# VR5-[[35, 37)]-{19}-[36] --> $s1
# VR5-[[38, 41)]-{20}-[40] --> $s1
# VR5-[[56, 58)]-{29}-[57] --> $s0
# VR6-[[27, 31)]-{15}-[30] --> $s1
# VR6-[[40, 42), [42, 47), [47, 53)]-{21}-[49, 52, 41] --> $s2
# VR6-[[55, 57)]-{28}-[56] --> $s1
# VR7-[[42, 44)]-{22}-[43] --> $s1
# VR7-[[44, 46)]-{23}-[45] --> $s1
# VR7-[[47, 51)]-{24}-[50] --> $s1
# VR7-[[52, 54)]-{26}-[53] --> $s0
# VR7-[[53, 55)]-{27}-[54] --> $s1
# VR8-[[48, 52)]-{25}-[51] --> $s3
App.substitute:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($fp)
	lw	$s2, 8 ($fp)
	lw	$s3, 12 ($s0)
	bnez	$s3, dispatch_notvoid186
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 308
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid186:
	move	$s4, $s1
	move	$s5, $s2
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 36 ($s4)
	jalr	$s3
	move	$s3, $a0
	lw	$s4, 16 ($s0)
	bnez	$s4, dispatch_notvoid187
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 309
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid187:
	move	$s0, $s1
	move	$s1, $s2
	move	$a0, $s4
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s4)
	lw	$s1, 36 ($s0)
	jalr	$s1
	move	$s0, $a0
	la	$s1, App_protObj
	move	$a0, $s1
	jal	Object.copy
	move	$s1, $a0
	jal	App_init
	move	$s2, $s1
	bnez	$s2, dispatch_notvoid188
	la	$s1, str_const0
	move	$a0, $s1
	li	$s1, 311
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid188:
	move	$s1, $s3
	move	$s3, $s0
	move	$a0, $s2
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s2)
	lw	$s1, 44 ($s0)
	jalr	$s1
	move	$s1, $a0
	move	$s0, $s1
	move	$s1, $s0
	move	$s0, $s1
	move	$a0, $s0
	j	__App.substitute_epilogue
__App.substitute_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s5, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 75
# VR0-[[0, 5), [5, 10), [10, 19), [19, 24), [24, 35), [35, 40), [40, 49), [49, 54), [54, 63), [63, 68), [68, 79), [79, 84), [84, 93), [93, 98), [98, 107), [107, 112), [112, 121), [121, 126), [126, 134)]-{0}-[17, 119, 3, 33, 77, 133, 47, 61, 91, 105] --> $s0
# VR1-[[1, 5), [5, 10), [10, 19), [19, 24), [24, 35), [35, 40), [40, 49), [49, 54), [54, 63), [63, 68), [68, 69)]-{1}-[68, 24] --> $s1
# VR2-[[2, 5), [5, 10), [10, 19), [19, 24), [24, 35), [35, 40), [40, 49), [49, 54), [54, 63), [63, 68), [68, 70)]-{2}-[69, 25] --> $s2
# VR3-[[3, 5), [5, 10), [10, 14)]-{3}-[4, 11, 13] --> $s3
# VR3-[[16, 17)]-{9}-[] --> $s3
# VR3-[[17, 19), [19, 24), [24, 30)]-{10}-[18, 26, 29] --> $s3
# VR3-[[32, 33)]-{17}-[] --> $s3
# VR3-[[33, 35), [35, 40), [40, 44)]-{18}-[34, 43, 41] --> $s3
# VR3-[[46, 47)]-{24}-[] --> $s3
# VR3-[[47, 49), [49, 54), [54, 58)]-{25}-[48, 55, 57] --> $s3
# VR3-[[60, 61)]-{31}-[] --> $s3
# VR3-[[61, 63), [63, 68), [68, 74)]-{32}-[70, 62, 73] --> $s3
# VR3-[[76, 77)]-{39}-[] --> $s1
# VR3-[[77, 79), [79, 84), [84, 88)]-{40}-[85, 87, 78] --> $s1
# VR3-[[90, 91)]-{46}-[] --> $s1
# VR3-[[91, 93), [93, 98), [98, 102)]-{47}-[101, 99, 92] --> $s1
# VR3-[[104, 105)]-{53}-[] --> $s1
# VR3-[[105, 107), [107, 112), [112, 116)]-{54}-[115, 113, 106] --> $s1
# VR3-[[118, 119)]-{60}-[] --> $s1
# VR3-[[119, 121), [121, 126), [126, 130)]-{61}-[127, 129, 120] --> $s1
# VR3-[[132, 133)]-{67}-[] --> $s1
# VR3-[[133, 135), [135, 140), [140, 144)]-{68}-[141, 143, 134] --> $s1
# VR3-[[146, 148)]-{74}-[147] --> $s0
# VR4-[[5, 7)]-{4}-[6] --> $s4
# VR4-[[7, 9)]-{5}-[8] --> $s4
# VR4-[[10, 13)]-{6}-[12] --> $s4
# VR4-[[13, 15)]-{7}-[14] --> $s4
# VR4-[[14, 16)]-{8}-[15] --> $s3
# VR4-[[19, 21)]-{11}-[20] --> $s4
# VR4-[[21, 23)]-{12}-[22] --> $s4
# VR4-[[24, 28)]-{13}-[27] --> $s4
# VR4-[[29, 31)]-{15}-[30] --> $s4
# VR4-[[30, 32)]-{16}-[31] --> $s3
# VR4-[[35, 37)]-{19}-[36] --> $s4
# VR4-[[37, 39)]-{20}-[38] --> $s4
# VR4-[[40, 43)]-{21}-[42] --> $s4
# VR4-[[43, 45)]-{22}-[44] --> $s4
# VR4-[[44, 46)]-{23}-[45] --> $s3
# VR4-[[49, 51)]-{26}-[50] --> $s4
# VR4-[[51, 53)]-{27}-[52] --> $s4
# VR4-[[54, 57)]-{28}-[56] --> $s4
# VR4-[[57, 59)]-{29}-[58] --> $s4
# VR4-[[58, 60)]-{30}-[59] --> $s3
# VR4-[[63, 65)]-{33}-[64] --> $s4
# VR4-[[65, 67)]-{34}-[66] --> $s4
# VR4-[[68, 72)]-{35}-[71] --> $s4
# VR4-[[73, 75)]-{37}-[74] --> $s1
# VR4-[[74, 76)]-{38}-[75] --> $s2
# VR4-[[79, 81)]-{41}-[80] --> $s2
# VR4-[[81, 83)]-{42}-[82] --> $s2
# VR4-[[84, 87)]-{43}-[86] --> $s2
# VR4-[[87, 89)]-{44}-[88] --> $s2
# VR4-[[88, 90)]-{45}-[89] --> $s1
# VR4-[[93, 95)]-{48}-[94] --> $s2
# VR4-[[95, 97)]-{49}-[96] --> $s2
# VR4-[[98, 101)]-{50}-[100] --> $s2
# VR4-[[101, 103)]-{51}-[102] --> $s2
# VR4-[[102, 104)]-{52}-[103] --> $s1
# VR4-[[107, 109)]-{55}-[108] --> $s2
# VR4-[[109, 111)]-{56}-[110] --> $s2
# VR4-[[112, 115)]-{57}-[114] --> $s2
# VR4-[[115, 117)]-{58}-[116] --> $s2
# VR4-[[116, 118)]-{59}-[117] --> $s1
# VR4-[[121, 123)]-{62}-[122] --> $s2
# VR4-[[123, 125)]-{63}-[124] --> $s2
# VR4-[[126, 129)]-{64}-[128] --> $s2
# VR4-[[129, 131)]-{65}-[130] --> $s2
# VR4-[[130, 132)]-{66}-[131] --> $s1
# VR4-[[135, 137)]-{69}-[136] --> $s0
# VR4-[[137, 139)]-{70}-[138] --> $s0
# VR4-[[140, 143)]-{71}-[142] --> $s0
# VR4-[[143, 145)]-{72}-[144] --> $s0
# VR4-[[144, 146)]-{73}-[145] --> $s1
# VR5-[[25, 29)]-{14}-[28] --> $s5
# VR5-[[69, 73)]-{36}-[72] --> $s1
App.gen_code:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s4, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($fp)
	lw	$s2, 8 ($fp)
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid189
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 316
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid189:
	la	$s4, str_const27
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 12 ($s4)
	jalr	$s3
	move	$s3, $a0
	lw	$s3, 12 ($s0)
	bnez	$s3, dispatch_notvoid190
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 317
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid190:
	move	$s4, $s1
	move	$s5, $s2
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s5, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 40 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid191
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 318
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid191:
	la	$s4, str_const28
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 12 ($s4)
	jalr	$s3
	move	$s3, $a0
	move	$s3, $s0
	bnez	$s3, dispatch_notvoid192
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 319
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid192:
	la	$s4, str_const29
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s4, 8 ($s3)
	lw	$s3, 12 ($s4)
	jalr	$s3
	move	$s3, $a0
	lw	$s3, 16 ($s0)
	bnez	$s3, dispatch_notvoid193
	la	$s4, str_const0
	move	$a0, $s4
	li	$s4, 320
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid193:
	move	$s4, $s1
	move	$s1, $s2
	move	$a0, $s3
	sw	$s4, 0 ($sp)
	addi	$sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s1, 8 ($s3)
	lw	$s2, 40 ($s1)
	jalr	$s2
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid194
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 321
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid194:
	la	$s2, str_const30
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid195
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 322
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid195:
	la	$s2, str_const31
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid196
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 323
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid196:
	la	$s2, str_const32
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid197
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 324
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid197:
	la	$s2, str_const33
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid198
	la	$s0, str_const0
	move	$a0, $s0
	li	$s0, 325
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid198:
	la	$s0, str_const34
	move	$a0, $s1
	sw	$s0, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s0, 8 ($s1)
	lw	$s1, 12 ($s0)
	jalr	$s1
	move	$s0, $a0
	move	$a0, $s0
	j	__App.gen_code_epilogue
__App.gen_code_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s5, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s4, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 6
# VR0-[[0, 8)]-{0}-[4, 6, 7] --> $s0
# VR1-[[1, 4)]-{1}-[3] --> $s1
# VR2-[[2, 6)]-{2}-[5] --> $s2
# VR3-[[3, 5)]-{3}-[4] --> $s3
# VR3-[[5, 7)]-{4}-[6] --> $s1
# VR3-[[7, 9)]-{5}-[8] --> $s1
App.init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($fp)
	lw	$s2, 8 ($fp)
	move	$s3, $s1
	sw	$s3, 12 ($s0)
	move	$s1, $s2
	sw	$s1, 16 ($s0)
	move	$s1, $s0
	move	$a0, $s1
	j	__App.init_epilogue
__App.init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

# web count: 2
# VR0-[[0, 1)]-{0}-[] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s0
VarListNE.isNil:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	li	$s0, 0
	move	$a0, $s0
	j	__VarListNE.isNil_epilogue
__VarListNE.isNil_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 2
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s1
VarListNE.head:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($s0)
	move	$a0, $s1
	j	__VarListNE.head_epilogue
__VarListNE.head_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 2
# VR0-[[0, 2)]-{0}-[1] --> $s0
# VR1-[[1, 3)]-{1}-[2] --> $s1
VarListNE.tail:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 16 ($s0)
	move	$a0, $s1
	j	__VarListNE.tail_epilogue
__VarListNE.tail_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 21
# VR0-[[0, 3), [3, 8), [8, 15), [15, 20), [20, 29), [29, 34), [34, 40)]-{0}-[1, 39, 27, 13] --> $s0
# VR1-[[1, 3), [3, 8), [8, 10)]-{1}-[2, 8, 9] --> $s1
# VR1-[[12, 13)]-{6}-[] --> $s1
# VR1-[[13, 15), [15, 20), [20, 24)]-{7}-[21, 23, 14] --> $s1
# VR1-[[26, 27)]-{13}-[] --> $s1
# VR1-[[27, 29), [29, 34), [34, 36)]-{14}-[34, 35, 28] --> $s1
# VR1-[[38, 39)]-{19}-[] --> $s1
# VR1-[[39, 41)]-{20}-[40] --> $s1
# VR2-[[3, 5)]-{2}-[4] --> $s2
# VR2-[[5, 7)]-{3}-[6] --> $s2
# VR2-[[9, 11)]-{4}-[10] --> $s2
# VR2-[[10, 12)]-{5}-[11] --> $s1
# VR2-[[15, 17)]-{8}-[16] --> $s2
# VR2-[[17, 19)]-{9}-[18] --> $s2
# VR2-[[20, 23)]-{10}-[22] --> $s2
# VR2-[[23, 25)]-{11}-[24] --> $s2
# VR2-[[24, 26)]-{12}-[25] --> $s1
# VR2-[[29, 31)]-{15}-[30] --> $s2
# VR2-[[31, 33)]-{16}-[32] --> $s2
# VR2-[[35, 37)]-{17}-[36] --> $s2
# VR2-[[36, 38)]-{18}-[37] --> $s1
VarListNE.print:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($s0)
	bnez	$s1, dispatch_notvoid199
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 36
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid199:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 28 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	bnez	$s1, dispatch_notvoid200
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 36
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid200:
	la	$s2, str_const2
	move	$a0, $s1
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	lw	$s2, 8 ($s1)
	lw	$s1, 12 ($s2)
	jalr	$s1
	move	$s1, $a0
	lw	$s1, 16 ($s0)
	bnez	$s1, dispatch_notvoid201
	la	$s2, str_const0
	move	$a0, $s2
	li	$s2, 37
	sw	$s2, 0 ($sp)
	addi	$sp, $sp, -4
	jal	void_disp_handler
dispatch_notvoid201:
	move	$a0, $s1
	lw	$s2, 8 ($s1)
	lw	$s1, 44 ($s2)
	jalr	$s1
	move	$s1, $a0
	move	$s1, $s0
	move	$a0, $s1
	j	__VarListNE.print_epilogue
__VarListNE.print_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 8
	jr	$ra

# web count: 6
# VR0-[[0, 8)]-{0}-[4, 6, 7] --> $s0
# VR1-[[1, 4)]-{1}-[3] --> $s1
# VR2-[[2, 6)]-{2}-[5] --> $s2
# VR3-[[3, 5)]-{3}-[4] --> $s3
# VR3-[[5, 7)]-{4}-[6] --> $s1
# VR3-[[7, 9)]-{5}-[8] --> $s1
VarListNE.init:
	addi	$sp, $sp, -8
	sw	$fp, 8 ($sp)
	sw	$ra, 4 ($sp)
	addi	$fp, $sp, 4
	## saving registers
	sw	$s0, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s1, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s2, 0 ($sp)
	addi $sp, $sp, -4
	sw	$s3, 0 ($sp)
	addi $sp, $sp, -4
	move	$s0, $a0
	lw	$s1, 12 ($fp)
	lw	$s2, 8 ($fp)
	move	$s3, $s1
	sw	$s3, 12 ($s0)
	move	$s1, $s2
	sw	$s1, 16 ($s0)
	move	$s1, $s0
	move	$a0, $s1
	j	__VarListNE.init_epilogue
__VarListNE.init_epilogue:
	## restoring registers
	addi $sp, $sp, 4
	lw	$s3, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s2, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s1, 0 ($sp)
	addi $sp, $sp, 4
	lw	$s0, 0 ($sp)
	lw	$ra, 0 ($fp)
	lw	$fp, 4 ($fp)
	addi	$sp, $sp, 16
	jr	$ra

